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SizedFIFO and Xilinx Distributed RAM

 
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patil.nikhil



Joined: 17 Aug 2007
Posts: 69
Location: University of Texas at Austin

PostPosted: Mon Jun 30, 2008 3:36 am    Post subject: SizedFIFO and Xilinx Distributed RAM Reply with quote

Hi,

SizedFIFO.v as implemented in the bluespec library is currently suboptimal for synthesis by the Xilinx XST tools, since the memory arr[] defined in module SizedFIFO cannot be mapped to Distributed RAM (also referred to as LUT-based RAM). I tried this with version 9.1.03i.

I just realized that the only reason for this is that the Xilinx compiler has a brain-dead algorithm for doing this distributed RAM inference. The tool could potentially map any memories with one write port, but it has a very simple algorithm for figuring this out. In particular, it does not realize that the following code needs only one write port.

Code:
if (x)
   arr[addr] <= data;
else if (y)
   arr[addr] <= data;


A simple transformation to:

Code:
if (x || y)
    arr[addr] <= data;


causes the distributed ram inference to work perfectly.

SizedFIFO.v suffers from exactly this problem. The following (very self-explanatory) patch takes care of this:

Code:
--- a/SizedFIFO.v 2008-06-19 15:24:49.000000000 -0500
+++ b/SizedFIFO.v 2008-06-30 02:27:19.000000000 -0500
@@ -101,6 +101,10 @@
           end // if (RST_N == 0)
         else
          begin
+            if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
+              begin
+                arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
+              end
             if (CLR)
               begin
                  head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
@@ -118,7 +122,7 @@
                    end
                  else
                    begin
-                      arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
+                      //arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
                       tail <= `BSV_ASSIGNMENT_DELAY next_tail;
                       D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head];
                       head <= `BSV_ASSIGNMENT_DELAY next_head;
@@ -151,7 +155,7 @@
                    // but be warnned that with test fifo overflow causes loss of new data
                    // while without test fifo drops all but head entry! (pointer overflow)
                    begin
-                      arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; // drop the old element
+                      //arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; // drop the old element
                       tail <= `BSV_ASSIGNMENT_DELAY next_tail;
                       ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
                       not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;


Thanks!
nikhil
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Mon Jun 30, 2008 10:16 am    Post subject: Thank you Reply with quote

Nikhil,

Thank you for this patch, and for bringing the issue to our attention.
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