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dealing with a top level differential clock

 
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tspalink



Joined: 05 Nov 2015
Posts: 12

PostPosted: Thu Jan 07, 2016 1:55 pm    Post subject: dealing with a top level differential clock Reply with quote

I am trying to put together a top level that takes in a differential clock, converts that to a single-ended clock and uses that to time some logic, which sets some LEDs.

Bluespec determines the LED outputs is clocked by a "clock not available at the module boundary".

Sine this is the top level, I do not actually care about this... What is the "right" way to do this -- meaning, how should I write a top level that takes in only a differential clock, and generates output signals that are single-ended clocked?

Code:
interface SysClk;
   interface Clock clock;
endinterface

(interface Top;
   method Bit#(8) leds;
endinterface

(* synthesize, no_default_clock, no_default_reset, always_ready = "leds" *)
module top(Clock sysclk_p, Clock sysclk_n, Reset rst, Top ifc);

   SysClk sysclk <- mkSysClk(sysclk_p, sysclk_n, rst);
   Reset reset <- mkAsyncReset(0, rst, sysclk.clock);

   Counters counters <- mkCounters(clocked_by sysclk.clock, reset_by reset);

   method leds = counters.leds;

endmodule
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Thu Jan 07, 2016 2:59 pm    Post subject: Re: dealing with a top level differential clock Reply with quote

BSC keeps track of the clock associated with every signal. A value can only be used in a rule that is executing on that clock. BSC will give an error if you write a rule that mixes logic from multiple clock domains. BSC will also warn, as it's doing here, when you export a value but don't export the clock that it's associated with. That's because, as I said, you wouldn't be able to write a rule that used the exported value, because there wouldn't be a clock for the rule to use.

In this case, there is a clock, but it's a differential pair. BSC doesn't recognize these as clocks, so it can't take that into account in its clock analysis. That might be a future improvement worth adding.

What you can do, though, is to remove the association to a specific clock. BSC allows values to be associated with no clock. This is useful for constants or for asynchronous values. Output wires to LEDs at the top level are a common example -- the values are going to be connected to LEDs which are not clocked.

For imported Verilog modules, you can specify that an output is unclocked by using a 'clocked_by' clause and specifying the reserved clocked name 'no_clock'.

For values created in BSV, there will always be an associated clock. So you'll need to use a clock-crossing module to cross the clocked value into the unclocked domain. That clock-crossing module can be implemented as a wire in this case, but we still need to explicitly instantiate it, to express in BSV that we are creating a signal that can be used without a clock. The BSC library has a module 'mkNullCrossingWire' which can be used for this. (BSC also has 'mkNullCrossingReg', which creates a register with read methods for both clock domains -- basically, a Reg and null-crossing wire in one -- if that is cleaner in your design.)

Code:
import Clocks::*;
...

  ReadOnly#(Bit#(8)) leds_noclock <- mkNullCrossingWire(noClock, counters.leds);

  method leds = leds_noclock;

...
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