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value method results in input ports in the verilog code

 
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akshayj



Joined: 19 Feb 2015
Posts: 10

PostPosted: Sat Feb 13, 2016 2:03 pm    Post subject: value method results in input ports in the verilog code Reply with quote

I have the following value method
Code:
method Vector#(64, Reg#(Pathsize)) send_Lr();
                return path_values_calculated;
 endmethod

where I have defined path_values_calculated and Pathsize as
Code:
Vector#(64, Reg#(Pathsize))      path_values_calculated <- replicateM(mkReg(0));
typedef UInt#(11) Pathsize;

In the verilog file generated I get 64 input ports of size 11 by the name of
Code:

// send_Lr_0__write_1             I    11
// send_Lr_1__write_1             I    11
// send_Lr_2__write_1             I    11
..
..

These input ports are undesired. How can I get rid of these input ports.
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Sat Feb 13, 2016 2:19 pm    Post subject: Re: value method results in input ports in the verilog code Reply with quote

You have written a method that doesn't return a value, it returns a Vector of 64 Reg interfaces. If you want to return a value, you should have this:
Code:
method Vector#(64, Pathsize) send_Lr();
  return readVReg(path_values_calculated);
endmethod

BSC interprets what you wrote as an interface of 64 Reg sub-interfaces, each having a _read and a _write method. BSC ought to give you a type error, because you said 'method' when it was really an interface, but unfortunately BSC doesn't do that yet.
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akshayj



Joined: 19 Feb 2015
Posts: 10

PostPosted: Sat Feb 13, 2016 2:36 pm    Post subject: Reply with quote

I got it.
Thanks a lot for your quick reply.
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akshayj



Joined: 19 Feb 2015
Posts: 10

PostPosted: Thu Feb 18, 2016 7:43 am    Post subject: Reply with quote

When I use
Code:
method Vector#(64, Pathsize) send_Lr();
  return readVReg(path_values_calculated);
endmethod

I get only one output port with a size of 64x11 bits= 704 bits.
But I want to have 64 separate output ports with 11 bits size each.

Do I need to write 64 separate methods and then return value by each method separately?
Or, Is there some other way by which I can achieve it in the generated verilog file?

I may have to move to higher values of 128 and 256, having a single output port with so large size is going to complicate my problem.
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Thu Feb 18, 2016 12:41 pm    Post subject: Reply with quote

When a BSV method has inputs or outputs that are a complex data type (like a struct or vector), this is represented in the generated Verilog by one port, whose width is the entire width of the data type.

We provide hooks into gtkwave and Novas/Verdi waveform viewers, to make the experience of looking at these values easier. This is built into the Bluespec Development Workstation (BDW) GUI. It will expand a struct or vector into separate signals, and it will display enums/tags by their source name (instead of the bit representation).

Of course, if you're using the Verilog in other situations, you might like to have separate ports. It is on our to-do list to create an attribute for telling BSC to represent the value with separate ports, rather than one port. In the mean time, we have a script that can be used after the fact to create a wrapper Verilog module that instantiates your module and connects it to separate ports. (This is in the release at lib/tcllib/bluespec/expandPorts.tcl.)

In this case, though, you can change your BSV code, so that there are separate ports for the output. Here's an example of an interface with separate ReadOnly sub interfaces, and a parent module that shows how to collect those outputs back up into a Vector.
Code:
typedef 4       N;
typedef Bit#(8) T;

interface Ifc;
  interface Vector#(N, ReadOnly#(T)) vec;
endinterface

(* synthesize *)
module mkMod (Ifc);
   Vector#(N, Reg#(T)) rgs <- replicateM(mkReg(0));

   interface vec = map(regToReadOnly, rgs);
endmodule

(* synthesize *)
module mkTB ();
   Ifc m <- mkMod;

   rule do_disp;
      Vector#(N, T) vals = map(readReadOnly, m.vec);
      $display("vals = ", fshow(vals));
      $finish(0);
   endrule
endmodule

This will generate a RDY signal for each output port. To avoid that, you can use the 'always_ready' attribute on the subinterface. The names of the ports in this example will be 'vec_0__read', 'vec_1__read', etc. If you prefer different names, you can use port-renaming attributes to change it.
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akshayj



Joined: 19 Feb 2015
Posts: 10

PostPosted: Thu Feb 18, 2016 4:19 pm    Post subject: Reply with quote

Thanks again for the timely reply.
It's nice to have separate output ports now.
Being greedy, I intend to have separate input ports as well for a Vector input.
I tried out the following
Code:
typedef 4       N;
typedef Bit#(8) T;

interface Ifc;
  interface Vector#(N, WriteOnly#(T)) vec_in;
  interface Vector#(N, ReadOnly#(T)) vec;
endinterface

This did generate the input ports in the verilog file.
But I am unable to find a way to use this interface inside the module. As I do not find any functions similar to the regToReadOnly.
Code:
(* synthesize *)
module mkMod (Ifc);
   Vector#(N, Reg#(T)) rgs_in <- replicateM(mkReg(0));
   Vector#(N, Reg#(T)) rgs <- replicateM(mkReg(0));
   // how to write the input values from vec_in into rgs_in
   interface vec = map(regToReadOnly, rgs);
endmodule

Also,I do not wish to instantiate a module to be able to read the values (using readReadOnly as was done in mkTB).
I am using the modules designed using BSV in System Generator. So I would prefer to synthesize every module independently (with separate input and output ports) and then integrate them in System Generator with other blocks of System Generator.
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Thu Feb 18, 2016 4:29 pm    Post subject: Reply with quote

There is no built-in function for converting from Reg to WriteOnly. But you could write this yourself:
Code:
function WriteOnly#(a) regToWriteOnly(Reg#(a) ifc);
   return (interface ReadOnly
              method _write = ifc._write;
           endinterface);
endfunction
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akshayj



Joined: 19 Feb 2015
Posts: 10

PostPosted: Fri Feb 19, 2016 2:01 pm    Post subject: Reply with quote

Thanks a lot again. One small typo, it should be
Code:
 ....
return(interface WriteOnly
....

Where can I find the code of the readReadOnly function, so that I can try to write a similar writeWriteOnly function myself. Because, now I am not able to figure out, how to write values into these WriteOnly interfaces from a testbench.
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Feb 22, 2016 3:08 pm    Post subject: Reply with quote

The source for readReadOnly() is not visible in the release. However I can show it here:
Code:
function a readReadOnly(ReadOnly#(a) r);
   return r;
end function

If you want to write a writeWriteOnly() function, it might look like this:
Code:
function Action writeWriteOnly(WriteOnly#(a) r, a val);
   return r._write(val);
endfunction

Or, if you prefer, this might be a friendlier way to write it (although it requires more typing, because you have to explicitly write action..endaction):
Code:
function Action writeWriteOnly(WriteOnly#(a) r, a val);
  action
    r <= val;
  endaction
endfunction
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