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latching data on negative edge of the system clock

 
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yashkarundia



Joined: 13 Oct 2015
Posts: 3

PostPosted: Mon Dec 28, 2015 6:30 am    Post subject: latching data on negative edge of the system clock Reply with quote

Hi. I want to latch some data available in a register(reg_ir) onto some other register(latched_reg_ir). As soon as the data in the lached_reg_ir register becomes equal to some value, I want my rule to fire.I referred the manual. It says that we need to use mkClockInverter. However, i am not able to understand the syntax for the same. Could someone help?
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 500

PostPosted: Sun Jan 03, 2016 3:52 pm    Post subject: Re: latching data on negative edge of the system clock Reply with quote

Why do you need to create a latch? I generally avoid that in BSV; if it's needed at the edges of a design (where Verilog submodules are imported or where the top of the BSV design connects to Verilog), then I would do that in the Verilog at the edges. However, this can be done in BSV if you need it. Here's some example code that might help show how:
Code:
import Clocks::*;

(* synthesize *)
module mkMod();
  Clock clk_inv <- invertCurrentClock;

/* The above is shorthand for this:

  Clock clk <- exposeCurrentClock;
  ClockDividerIfc inv <- mkClockInverter;
  Clock clk_inv = inv.slowClock;
*/

  // Register clocked by 'clk'
  Reg#(Bool) rg1 <- mkRegU;

/* The above is equivalent to this:

  Clock clk <- exposeCurrentClock;
  Reg#(Bool) rg1 <- mkRegU (clocked_by clk);
*/

  // Register clocked by 'clk_inv'
  Reg#(Bool) rg2 <- mkRegU(clocked_by clk_inv);

  // Any registers clocked by the inverted clock
  // are considered by BSC to be in separate clock domains.
  // To cross data from the 'clk' domain to 'clk_inv' domain,
  // you will need to instantiate a clock-crossing module.
  // This can be a 'null' crossing module, that is just a wire,
  // as long as you are sure that no crossing logic is needed
  // (BSC will not check this for you):
  //
  ReadOnly#(Bool) w_rg1_crossed <- mkNullCrossingWire(clk_inv, rg1);

  // Now you can write a rule in the 'clk_inv' domain that uses
  // the crossed value
  //
  rule r;
    rg2 <= w_rg1_crossed;
  endrule

/* Note that you can also use mkNullCrossingReg to instantiate a
   register whose value is available in two domains, eliminating
   the need for an explicit crossing module:

   CrossingReg#(Bool) rg1 <- mkNullCrossingRegU(clk_inv);

   rule r;
      rg2 <= rg1.crossed;
   endrule
*/

endmodule
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