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Checking address conflict in RegFile

 
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mcadler



Joined: 20 Aug 2007
Posts: 18

PostPosted: Mon Jul 06, 2015 12:16 am    Post subject: Checking address conflict in RegFile Reply with quote

It appears that Altera's LUT memory (MLAB) does not support returning old data on the read port when configured with unregistered reads. This is the mode that is needed to support use of RegFile sub() results in the same cycle as the sub() call. When write to and read from the same address happen in a single cycle the result appears to be unpredictable. The altsyncram and altdpram megafunctions document this.

Clearly this is a problem for RegFile semantics.

I tried to write a wrapper around RegFile that at least detects the conflict at run time in Bluesim. The problem I'm having is sub() is a pure method and I can't think of any way to expose the fact that it is called and the address to a method that can compare the address with a same-cycle upd() and call $display or $finish. Any suggestions? Some BDPI hack is the only thing I can think of so far, though that will work only in Simulation.

It would also be good to hear from anyone who knows of any Stratix V memory mode that has RegFile semantics.
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 495

PostPosted: Mon Jul 06, 2015 12:09 pm    Post subject: Re: Checking address conflict in RegFile Reply with quote

I think you would need to create a variation where the "sub" method is ActionValue, so that there is an EN port to indicate when it's being used. Or, the Verilog could return "X" in those cases and you'd need some other way to look for X if it eventually gets used elsewhere in the design.

Unfortunately, value methods are always being computed in the Verilog implementation, but the value may only be used in some cases. BSC doesn't keep track of this, but we'd like to keep track of it, to implement a number of features. For instance, in Bluesim, if some logic does a divide-by-zero, we'd like to know whether that's a real error to report or if the value is unused (Verilog simulation handles this by returning "X"). There are a number of situations where we'd like to write a dynamic error check in the Verilog, but we'd need to know the conditions under which that logic is actually used, otherwise the error would be reported too often. So I feel your pain, but unfortunately there's no feature available now that provides that information for you.
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mcadler



Joined: 20 Aug 2007
Posts: 18

PostPosted: Mon Jul 06, 2015 3:31 pm    Post subject: Reply with quote

Indeed it would be nice to have some way of checking the state.

I finally concluded in this case that dropping RegFile read-before-write semantics was going to be a debugging nightmare. I rewrote RegFile.v to delay the write internally by a cycle and bypass reads during the cycle the memory is actually updated. Hopefully it won't affect timing much. I think it will be ok since I didn't introduce any dependence between the incoming write and the incoming read. The bypass comparison is against the buffered write request.

I'll give you a patch after working with it for a while. A patch was needed already because Quartus doesn't infer multiple read ports properly. I had to replicate the LUTRAM explicitly and write all 5 copies by hand. Quartus does properly delete unused copies.
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