bluespec.com Forum Index bluespec.com
Bluespec Forums
 
 FAQFAQ   SearchSearch   MemberlistMemberlist   UsergroupsUsergroups   RegisterRegister 
 ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

Verilog attributes

 
Post new topic   Reply to topic    bluespec.com Forum Index -> Designing with BSV's Rules, Interfaces, ...
View previous topic :: View next topic  
Author Message
oarcas



Joined: 24 Feb 2011
Posts: 9

PostPosted: Mon Jul 21, 2014 10:20 am    Post subject: Verilog attributes Reply with quote

Hi,

Is it possible to put attributes to BSV modules (wires, registers, etc.) so that these attributes remain in the Verilog code?

I don't know if this feature exists, but it would be very useful when synthesizing the hardware with ISE or Quartus (for instance, putting the Xilinx "KEEP" attribute to some wires).

Thanks,

Oriol
Back to top
View user's profile Send private message
quark
Site Admin


Joined: 02 Nov 2007
Posts: 496

PostPosted: Mon Jul 21, 2014 1:55 pm    Post subject: Re: Verilog attributes Reply with quote

Hi Oriol,

There is not a way to specify Verilog attributes in the BSV source.

Some BSV objects allow the "doc" attribute, which places a comment in the generated Verilog. And that can be used to place a comment attribute in the Verilog. Or to at least put a place-holder into the generated Verilog, so that a post-processing script can find the comment and replace it with an attribute. (The -verilog-filter flag can be used to automatically run a script to post-process the Verilog.)

The "doc" attribute is not available for most wire signals, though. What kind of signals do you want to use the KEEP attribute for? Can a post-processing script identify them?

In the BSV source, if you instantiate a Wire or a Reg, BSC doesn't generate a module instantiation for that in the Verilog (like it does with other module instantiations) but instead BSC inlines the module into parent. This is the default behavior, but if you want BSC to instantiate Reg and Wire modules in the generated Verilog, there are hidden flags -inline-reg, -inline-rwire, and -inline-creg that can be used with the -no prefix. So you can use -no-inline-rwire to preserve Wire modules in the generated Verilog. This could be helpful for directing synthesis tools to preserve the ports on that boundary, or helpful for post-processing scripts to find the ports.

Another way to get a handle on logic from the BSV source is to instantiate a module (like a Wire or a Reg) and connect the logic to an input of that module. You could even instantiate your own Verilog module. For example, you could take the RWire.v file and edit it to make a module that has the KEEP attribute inside:
Code:
module KeepWire(WGET, WHAS, WVAL, WSET);
   parameter width = 1;

   (* KEEP = "TRUE" *)
   input [width - 1 : 0]    WVAL;
   input                    WSET;
   ...
endmodule

And then you could import this module and instantiate it in your design, using it in the data path that you want to keep.

There is also the Bluetcl program available in the release. This is a Tcl shell with commands for loading BSV packages and modules, and querying information about them. Bluetcl can be used to help with synthesis, by writing scripts that extract information about the design -- such as identifying clocks, or identifying ports or modules. This can be used to output synthesis directives, or to help post process the generated Verilog.
Back to top
View user's profile Send private message
oarcas



Joined: 24 Feb 2011
Posts: 9

PostPosted: Sun Dec 21, 2014 8:40 am    Post subject: Re: Verilog attributes Reply with quote

Hi Quark. With a bit of delay, thanks for your reply.

Recently I needed to mark some registers as "KEEP = TRUE", so I revisited this topic. I share how I implemented the (* doc *)-based solution.

I created two new modules, called mkKeepReg, mkKeepRegU and mkKeepDReg:

Code:
import DReg::*;

module mkKeepReg#(t v) (Reg#(t)) provisos(Bits#(t, t_sz));
    (* doc = "(* KEEP = TRUE *)" *)
    Reg#(t) r <- mkReg(v);
    return r;
endmodule

module mkKeepRegU(Reg#(t)) provisos(Bits#(t, t_sz));
    (* doc = "(* KEEP = TRUE *)" *)
    Reg#(t) r <- mkRegU;
    return r;
endmodule

module mkKeepDReg#(t def) (Reg#(t)) provisos(Bits#(t, t_sz));
    (* doc = "(* KEEP = TRUE *)" *)
    Reg#(t) r <- mkDReg(def);
    return r;
endmodule


These modules generate Verilog regs with a "(* KEEP = TRUE *)" comment before. Using a small sed line these "// (* KEEP = TRUE *)" can be converted into "(* KEEP = "TRUE" *)" Verilog attributes, so that Xilinx understands them:

Code:
sed 's/\/\/ *( *\* *KEEP *= *TRUE *\* *)/(* KEEP = "TRUE" *)/g' < $inf > $outf


I still think a (* VATTR = "name, value" *) BSC attribute would be more elegant, but anyway the workaround is not that hard Wink
Back to top
View user's profile Send private message
Display posts from previous:   
Post new topic   Reply to topic    bluespec.com Forum Index -> Designing with BSV's Rules, Interfaces, ... All times are GMT - 4 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
You can attach files in this forum
You can download files in this forum
bluespec.com topic RSS feed 


Powered by phpBB © 2001, 2005 phpBB Group
Protected by Anti-Spam ACP