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BVI wrap STD_LOGIC_VECTOR bit order

 
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garethlloyd



Joined: 19 Mar 2014
Posts: 12

PostPosted: Tue Jul 08, 2014 10:37 am    Post subject: BVI wrap STD_LOGIC_VECTOR bit order Reply with quote

Does the bit order matter? Do I need to make sure the port is 31 downto 0 rather than 0 to 31?
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quark
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Joined: 02 Nov 2007
Posts: 499

PostPosted: Tue Jul 08, 2014 1:22 pm    Post subject: Re: BVI wrap STD_LOGIC_VECTOR bit order Reply with quote

My suggestion is to write a small example and see.

If you have a VHDL module that you want to instantiate in your design, you can do this by writing an import-BVI block. BSC will generate a Verilog file with a module instantiation. It is then the simulation or synthesis tool that is responsible for connecting the Verilog and VHDL modules.

In the generated Verilog the LSB will always be the 0 and the MSB will be the size of the vector minus one (in this case 31). It sounds like VHDL allows you to express this (with 31 downto 0) but also allows you to assign the MSB to 0 (with 0 to 31). My guess, then, is that the VHDL numbering is only meaningful inside the VHDL code. The simulation or synthesis tool will (I assume) connect the MSB to the MSB. In Verilog that will be index 31. The declaration in VHDL will determine whether that bit is indexed as 0 or 31, but in either case it's still the MSB. You'll need to make sure that the BSV code is operating on the bits in the correct order.

My suggestion, again, is to write a simple example so that you can observe how it works.
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