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Register initialization in generated verilog.

 
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tomahawkins



Joined: 14 Dec 2012
Posts: 21

PostPosted: Thu Mar 14, 2013 9:59 pm    Post subject: Register initialization in generated verilog. Reply with quote

I'm having an issue with BSC generated Verilog in Xilinx XST. It's really a bug with XST, but since Xilinx is so slow to fix such problems, I thought I'd see if the Bluespec community can offer up any quick workarounds.

The issue is I'm tying off RST_N to 1 and relying on Xilinx to initialize all state elements to zero. In the design there are a handful of registers that, once enabled, are assign constant values. With RST_N set to 1, after constant propagation, XST would see something like this:

Code:

reg x;
wire x$EN = ...;
always @ (posedge CLK)
  if (x$EN) x <= 1'b1;


To you and I, this would appear to be a register. But to XST, it thinks it's a constant:

Code:

assign x = 1'b1;


Xilinx does have a way to specify initial conditions in *.xcf files. The problem is XST does register inference before it reads the constraints file. Then when it sees the INIT constraint, it errors out because the register was never inferred.

The one thing that does work is to add the initial values to the Verilog -- not with an "initial" statement, but with some 2001 syntax I didn't know existed:

Code:

reg x = 1'b0;  // The initial value for register x.
wire x$EN = ...;
always @ (posedge CLK)
  if (x$EN) x <= 1'b1;


Has anyone had to tackle this problem before? I can easily write a script to patch up the BSC generated Verilog. With more work I could parse the Verilog, extract the initial values from the RST_N branches, then rewrite the AST with the initial conditions. But it would be so much easier if BSC had a switch to handle this syntax. I know it's ugly business supporting all the kludgy synthesis tools, but it seems like having a concrete way to specify initial conditions in the RTL is a good feature to have.

-Tom
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draenor



Joined: 15 Aug 2007
Posts: 7

PostPosted: Fri Mar 15, 2013 1:32 pm    Post subject: Reply with quote

Hi Tom,

I am curious why you are tying off the reset signal, yet need to rely on the "reset" or power-on value, essentially. It seems rather fragile to rely on the power-on value for a reset.

What exactly are you trying to do?

Best Regards
-Todd
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tomahawkins



Joined: 14 Dec 2012
Posts: 21

PostPosted: Mon Mar 18, 2013 2:23 pm    Post subject: Reply with quote

For our application, the Xilinx GSR is good enough. Since the FPGA is configured with the initial values, there's really no need for a global reset. In fact needlessly adding a global reset wastes a lot of routing resources. Here's a good Xilinx whitepaper on the topic:

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

For this reason, it would be nice to have a switch that generates code with the initial values, and possibly even gets rid of the global resets.

-Tom
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draenor



Joined: 15 Aug 2007
Posts: 7

PostPosted: Wed Mar 20, 2013 11:22 am    Post subject: Reply with quote

Hi Tom,

There is a compiler switch to remove the inlining of registers and then you can redefine the RegN.v module that lives in $BLUESPECDIR/Verilog to get the desired effect. The ports of RegN.v cannot be modified, however, you can leave the RST pin floating and Xilinx synthesis will do-the-right-thing. Simply create your own RegN.v version and source that with Xilinx synthesis.

There are two methods of throwing the flag. You can throw it globally, giving the flag to the bsc command line, or you can throw it on a per-synthesized module basis via the options attribute.

The flag is:
Code:
-no-inline-reg


I have attached an example module to show how it can be used in the local manner.



test.bsv
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 Filename:  test.bsv
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