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Synthesizable assertions

 
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Thu Aug 09, 2007 5:57 pm    Post subject: Synthesizable assertions Reply with quote

Hello,

I'm wondering if Bluespec is planning on supporting run-time "whitebox" debugging features in the future. In particular, I noticed that OVLAssertions are already supported by the compiler. It's crossed my mind to actually substitute some of these simulation-only modules with my own that can actually be synthesized and used to trigger errors during runtime on an FPGA. This type of feature would absolutely be great since our CPU verification constitutes running billions of instructions.

Thanks,
Eric
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nikhil
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Joined: 23 Jul 2007
Posts: 14
Location: Waltham, MA

PostPosted: Thu Aug 09, 2007 7:53 pm    Post subject: Reply with quote

Yes, we do plan to have stronger support for assertions in the future, but
we have not yet made a concrete plan for it.

We actually have protototype code for reading SVA (SystemVerilog
Assertions) placed inside BSV source code, and for synthesizing them
into RTL alongside the design RTL. But we need to have some serious
engineering resources to make it product-worthy. At this point it's
a little difficult to predict when that might be, but we recognize the
growing importance of assertion-based design and verification, and
we will surely address it.

Regards,

Nikhil
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