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Reg Problem

 
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flashdisk



Joined: 29 May 2012
Posts: 56

PostPosted: Tue Jun 19, 2012 10:59 am    Post subject: Reg Problem Reply with quote

hey,

Code:
interface Ifc_Pmult3;


method Action mult1(Bit#(10) x, Bit#(10) y);
method Bit#(10) mult2();
method Bit#(4) exp(Bit#(4) exp1, Bit#(4) exp2);


endinterface

(* synthesize *)

module mkPmult3(Ifc_Pmult3);

Reg#(Bit#(10)) result<-mkReg(0);



////////////////////////////////////////////////////////////



method Action mult1(Bit#(10) x, Bit#(10) y);

result<=x*y; // it does not enter in result the x*y value why?

endmethod



////////////////////////////////////////////////////////////
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quark
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Joined: 02 Nov 2007
Posts: 500

PostPosted: Tue Jun 19, 2012 11:49 am    Post subject: Re: Reg Problem Reply with quote

Your module looks fine. What makes you think that it's not assigning to the register?
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flashdisk



Joined: 29 May 2012
Posts: 56

PostPosted: Tue Jun 19, 2012 12:24 pm    Post subject: Reply with quote

because i send bit x and bit y which are differnet from zero lets say 3 and 2 in binary but i get zero in the result when i run the testbench!
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quark
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Joined: 02 Nov 2007
Posts: 500

PostPosted: Tue Jun 19, 2012 12:37 pm    Post subject: Reply with quote

How are you providing the values to x and y? Are you using a test bench written in BSV? Are you simulating in Bluesim or in Verilog?

If you are simulating in Verilog and using your own driver, you will need to assert the EN_mult1 port of the module. The method is only active when that signal is asserted. Alternatively, you can put the "always_enabled" attribute on the method, to have BSC generate a Verilog module without this port (with the assumption that the method is always asserted).
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flashdisk



Joined: 29 May 2012
Posts: 56

PostPosted: Tue Jun 19, 2012 12:40 pm    Post subject: Reply with quote

I am using a testbench file in which I had declared the following:
x='b0011;
y='b0101;

and I sent them to the method to do the computation.
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quark
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Joined: 02 Nov 2007
Posts: 500

PostPosted: Tue Jun 19, 2012 12:57 pm    Post subject: Reply with quote

I need more information. If you can provide the source code for the test bench, that would be helpful. Also, it would help to know more about how you are simulating and what specifically you are doing to observe that the result is 0. Are you simulating in Bluesim or Verilog? Are you generating a VCD file and looking at the waveform or ...?

I presume that you have a rule in your test bench which is calling the method. So, the first thing to check is whether the rule is executing.

Do you observe that the rule is executing? You can observe this in Bluesim with command-line options. You can also observe this in a waveform viewer from the VCD file generated by either Bluesim or Verilog simulation. You might want to run BSC with the -keep-fires flag to preserve rule execution signals in the generated Verilog. Specifically, this flag will keep the signals CAN_FIRE_rulename and WILL_FIRE_rulename in the generated Verilog.

You may also want to observe whether the method is executing. In the waveform viewer you can look for the enable signal, EN_mult1.
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flashdisk



Joined: 29 May 2012
Posts: 56

PostPosted: Tue Jun 19, 2012 1:09 pm    Post subject: Reply with quote

I am simulating in bluesim and I don't make waveforms just compiling and running the testbench and the code it self and observing the results on the output windows of the compiler ,I will bring for you the testchbench file and the code as soon as possible because I don't have it right now and thanks for your help Razz
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flashdisk



Joined: 29 May 2012
Posts: 56

PostPosted: Mon Jun 25, 2012 3:29 am    Post subject: Reply with quote

I posted it in new topic!
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