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SyncFIFO synthesis issue

 
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laplander



Joined: 27 Jun 2011
Posts: 1

PostPosted: Tue Jun 28, 2011 6:06 am    Post subject: SyncFIFO synthesis issue Reply with quote

As stated in Release_notes_2011.04

Changes to SyncFIFO and SyncFIFOLevel (rg C.9.7)
Added output register to improve timing for synthesis. Latency remains the same.

However Synplify still complains about it
Code:

@N: CL134 :"Bluespec/latest/lib/Verilog/SyncFIFO.v":109:3:109:8|Found RAM fifoMem, depth=16, width=65
@A:"Bluespec/latest/lib/Verilog/SyncFIFO.v":165:3:165:8|Feedback mux created for signal dDoutReg[64:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area


This patch does fix this warning and improve timing
Code:

@@ -169,6 +171,7 @@
              dGDeqPtr     <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 2) {1'b0}} ;
              dGDeqPtr1    <= `BSV_ASSIGNMENT_DELAY {{indxWidth {1'b0}}, 2'b11 } ;
              dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
+            dDoutReg <= `BSV_ASSIGNMENT_DELAY {dataWidth{1'b0}};
           end // if (dRST_N == 0)
         else
            begin
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ewc



Joined: 08 May 2007
Posts: 31

PostPosted: Wed Jun 29, 2011 10:21 am    Post subject: Reply with quote

Thanks for your question.

The exclusion of the dDoutReg in the reset path was a deliberate design decision, since there is no need to reset data elements of a fifo. As another example see our Verilog SizedFIFO.v model.

I am partly surprised that Synplify has trouble with this code style, since the model is simply a D-Flop without a reset. You patch is functionally correct and I can recommend that you use it during Synplify synthesis.

I've included another patch below, which separates resetable and non-resetable flops into different always blocks. I hope that Synplify deals with this style better. Can you try this patch and report Synplify's results.

Thanks
Ed.

Code:

--- SyncFIFO.v   (revision 24442)
+++ SyncFIFO.v   (working copy)
@@ -175,7 +175,6 @@
               if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin
                  dGDeqPtr     <= `BSV_ASSIGNMENT_DELAY dGDeqPtr1 ;
                  dGDeqPtr1    <= `BSV_ASSIGNMENT_DELAY incrGrayP( dGDeqPtr1 );
-                 dDoutReg     <= `BSV_ASSIGNMENT_DELAY fifoMem[dDeqPtrIndx] ;
                  dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1;
               end
               else if (dDEQ && !dNextNotEmpty) begin
@@ -184,6 +183,13 @@
            end // else: !if(dRST_N == 0)
      end // always @ (posedge dCLK or negedge dRST_N)
 
+   always @(posedge dCLK)
+     begin
+        if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin
+           dDoutReg     <= `BSV_ASSIGNMENT_DELAY fifoMem[dDeqPtrIndx] ;
+        end
+     end
+
     // Dequeue pointer synchronized to sCLK
     always @(posedge sCLK  or negedge sRST_N)
       begin

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Ed C
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