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Inout verilog generation

 
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kfleming



Joined: 20 Feb 2010
Posts: 5

PostPosted: Mon Mar 29, 2010 9:45 pm    Post subject: Inout verilog generation Reply with quote

Why does bluespec generate this sort of notation for inouts? I was just curious.

module mk_model_Wrapper(.ddrWires_dq(m_vp_llpi_phys_plat_ddr_controller_fpga_0_DDR_SDRAM_DDR_DQ),
.ddrWires_dqs(m_vp_llpi_phys_plat_ddr_controller_fpga_0_DDR_SDRAM_DDR_DQS),

CLK,
RDY_clock_wire,

RST_N,
RDY_reset_n_wire,

ledsWires_LED,

switchesWires_SWITCH,
EN_switchesWires_switches_wire,
RDY_switchesWires_switches_wire,

serialWires_serial_rx_serial_rx,
EN_serialWires_serial_rx,
RDY_serialWires_serial_rx,

serialWires_serial_cts_serial_cts,
EN_serialWires_serial_cts,
RDY_serialWires_serial_cts,

serialWires_serial_tx,

serialWires_serial_rts,

serialWires_serial_dtr,

ddrWires_ck_p,

ddrWires_ck_n,

ddrWires_a,

ddrWires_ba,

ddrWires_ras_n,

ddrWires_cas_n,

ddrWires_we_n,

ddrWires_cs_n,

ddrWires_ce,

ddrWires_dm);
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 495

PostPosted: Mon Mar 29, 2010 10:56 pm    Post subject: Re: Inout verilog generation Reply with quote

In a port list, multiple ports could actually be referring to the same inout signal. You cannot use an "assign" statement to connect two inout signals. The only way that Verilog allows for multiple ports to share the same net is with this syntax:
Code:
module modName (.port1(inout_net), .port2(inout_net));

Here, the module has ports named "port1" and "port2" which are visible to the outside world, but the module has a single internal net called "inout_net" which is inout signal that is referenced inside the module.
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