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Pack/Unpack functions

 
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muem



Joined: 04 Nov 2009
Posts: 3

PostPosted: Tue Jan 26, 2010 7:15 am    Post subject: Pack/Unpack functions Reply with quote

Hi all,

I have a question about pack/unpack functions.

In one of my modules I have a type of the form
Code:
Vector#(4, Reg#(Vector#(4, Bit#(8))))
which just represents a 4x4 Byte matrix with 4 registers each holding a Word.
For the interface of this module I don't want to use this 4x4 Byte representation. Instead I want to use a flattened 1x16 Byte vector (i.e. Vector#(16, Byte)).

Currently I am using the following code to store the flattened 1x16 Byte input vector in the 4x4 Byte matrix:
Code:
matrix[0] <= unpack({input[3], input[2], input[1], input[0]});
matrix[1] <= unpack({input[7], input[6], input[5], input[4]});
matrix[2] <= unpack({input[11], input[10], input[9], input[8]});
matrix[3] <= unpack({input[15], input[14], input[13], input[12]});

And this one to get back the 1x16 Byte output vector from the 4x4 Byte matrix:
Code:
outVec = unpack({pack(matrix[3]), pack(matrix[2]), pack(matrix[1]), pack(matrix[0])});

For all of you who don't know yet what I had implemented (Don't think it's hard to guess anymore Wink ): It's a simple AES module. Right now I am trying to find the best area/performance tradeoff and was asking myself whether there is a better way to handle this one-dimensional to two-dimensional "conversion" and vice versa? For instance it would be possible to create an output vector and assign one byte after the other like:
Code:
outVec[0] = matrix[0][0];
outVec[1] = matrix[0][1];
outVec[2] = matrix[0][2];
...

Would this make any differences to the previous version? Or is the way using the pack/unpack functions the most efficient one?

Thanks, Mike
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Wed Jan 27, 2010 11:10 am    Post subject: Reply with quote

Mike,

Quote:
In one of my modules I have a type of the form
Code:
Vector#(4, Reg#(Vector#(4, Bit#(8))))

which just represents a 4x4 Byte matrix with 4 registers each holding a Word.


Incidentally, the declaration above actually specifies 4 registers, each holding 4 single-byte words. Perhaps you meant:
Code:
Vector#(4,Vector#(4,Reg#(Bit#(8))))


The Vector package's readVReg and writeVReg functions are useful for working with these kinds of vectors-of-register declarations, BTW.

As for the pack/unpack variations, these should all generate permutations of wires with no other logic, so I would not expect any area or performance differences between them.

Jeff
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muem



Joined: 04 Nov 2009
Posts: 3

PostPosted: Wed Jan 27, 2010 11:44 am    Post subject: Reply with quote

jnewbern wrote:
Incidentally, the declaration above actually specifies 4 registers, each holding 4 single-byte words.

Maybe my description was a little bit irritating but that type is exactly what I wanted to create. With your suggestion (4x4 register array each holding a byte) I would have been able to "operate" on each byte separately but I am only operating on words. Hence the 4 registers each holding 4 single-byte words work perfectly for me.
jnewbern wrote:
The Vector package's readVReg and writeVReg functions are useful for working with these kinds of vectors-of-register declarations, BTW.

Thanks, I already found them in the reference guide. These are really useful functions when operating on vectors.
jnewbern wrote:
As for the pack/unpack variations, these should all generate permutations of wires with no other logic, so I would not expect any area or performance differences between them.

Thanks for confirming my assumptions,
Mike
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