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Instruction set to memory

 
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tyeowkwa



Joined: 09 Feb 2010
Posts: 7

PostPosted: Sun Feb 28, 2010 7:12 pm    Post subject: Instruction set to memory Reply with quote

Is there a way to write a list of processor instructions and data into memory.
so that I can used a program counter to move thru these instruction and execute them?

e.g.

mem[0] = { MOVI a, 123};
mem[1]= { LD a,b};



mem[100]= data 1;
mem[101]= data 2;

etc...
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Mon Mar 01, 2010 11:47 am    Post subject: Reply with quote

What sort of memory are you using? If you are using a mkRegFile, then there is mkRegFileLoad that allows you to supply a Verilog-format memory initialization file.
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tyeowkwa



Joined: 09 Feb 2010
Posts: 7

PostPosted: Mon Mar 01, 2010 9:38 pm    Post subject: Reply with quote

thanks for the replies. And yes I am using Reg type mem. Is there any examples for the given mentioned? So that i can have a better understanding how to use it?
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Mon Mar 01, 2010 10:06 pm    Post subject: Reply with quote

The RegFile variants are described in the Bluespec Language Reference Manual in section C.1.1.

The file format is the same standard Verilog file format used to load data using the Verilog $readmemh(), $readmemb(), etc. system calls. The format is described in section 17.2.8 of the Verilog LRM (available here http://www.boyd.com/1364/1364-2005-d2.pdf.gz).

For example, if you instantiate a RegFile this way:

Code:
RegFile#(Address, Data) mem <- mkRegFileFullLoadBin("test_program.bin");


You can load a file called "test_program.bin" that might look like:

Quote:
010000000000 // address: 0 // LDC R0
000000000001 // address: 1 // 1
010000010000 // address: 2 // LOOP1: LDC R1
000000000001 // address: 3 // 1
010001100000 // address: 4 // LOOP2: LDD R2
000000111001 // address: 5 // VAR
010010100000 // address: 6 // LDIN R2
000000111010 // address: 7 // REF1
010011110000 // address: 8 // LDIN2 R3
000000111011 // address: 9 // REF2
000001000000 // address: 10 // JMP
000000001100 // address: 11 // MARK1
000011000000 // address: 12 // MARK1: JZ
000000001110 // address: 13 // MARK2
000010000000 // address: 14 // MARK2: JC
000000010000 // address: 15 // MARK3
000100000000 // address: 16 // MARK3: JN
000000010010 // address: 17 // MARK4
000101000000 // address: 18 // MARK4: JO
000000010100 // address: 19 // MARK5
000110000000 // address: 20 // MARK5: JNC
000000010110 // address: 21 // MARK6
001000000000 // address: 22 // MARK6: JNN
000000011000 // address: 23 // MARK7
001001000000 // address: 24 // MARK7: JNO
000000011010 // address: 25 // MARK8
111000101110 // address: 26 // MARK8: ADD R2 R3 R2
111001101110 // address: 27 // ADDC R2 R3 R2
111011101110 // address: 28 // SUBC R2 R3 R2
101000100010 // address: 29 // NEG R2 R2
110000101110 // address: 30 // AND R2 R3 R2
110010101110 // address: 31 // OR R2 R3 R2


Note, the addresses here are just comments. You can specify addresses explicitly using the @ syntax described in the Verilog LRM.

There are also hexadecimal variants so that you can use hex format data if you prefer.
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tyeowkwa



Joined: 09 Feb 2010
Posts: 7

PostPosted: Wed Mar 03, 2010 4:44 am    Post subject: Reply with quote

Thanks. for this code:
RegFile#(Address, Data) mem <- mkRegFileFullLoadBin("test_program.bin");

how do we retrieve the value back from the memory as in this case "mem"?

can we just write "store <= mem[0]; "



In specifying the address is it we do this in the file?

@211 00110000
@212 00000011

:
:
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Wed Mar 03, 2010 8:06 am    Post subject: Reply with quote

The interface methods of mkRegFileFullLoad are the same as mkRegFileFull. The only difference is the initialization from the file.

The file format is the standard Verilog memory file format, described in the manual I linked to earlier. You can use @address to specify the address, but addresses are assumed to increment linearly, so it is enough to specify only the first address in a memory region.
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