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Multi-clock domain question

 
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Tue Jun 26, 2007 11:12 pm    Post subject: Multi-clock domain question Reply with quote

Hello,

I'm trying to utilize the multiple clock domain features of Bluespec. In particular, my module imports 2 clocks (100Mhz, 200MHz w/ aligned clock edges) and transfers info between those domains. The reference guide suggests the use of mkSyncRegToSlow, mkSyncRegToFast when the clocks are aligned, however, it seems that I'm required to generate a divided clock off of an existing clock in order to use such primitives. Instead, I want to somehow convey to the compiler that my 2 imported clocks are already aligned and that the mkSyncRegs should operate off of those.

Is there a way to do this? Or maybe there's a better alternative I'm not thinking of... I'm currently working with FPGAs, and it's necessary for me to use special aligned clocks coming from a generator.

Thanks,
Eric Chung
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SteveA



Joined: 03 May 2007
Posts: 32

PostPosted: Wed Jun 27, 2007 12:41 pm    Post subject: Reply with quote

Hi Eric,

The compiler itself doesn't know or need to know the relative speed of the clocks. Basically the compiler is just ensuring that signals from one clock domain are not cross connected to signals of another clock domain.. But since the compiler can't really enforce that you provide appropriate clocks, you basically need to know this yourself...

You can use mkSyncReg, mkSyncRegToCC and mySyncRegFromCC, which are in the reference manual, but not superbly explained. They are double registers (see example below). On the otherhand, if you are confident your edges are alinged well (as we are with our connection to Eve boxes Wink, you could create your own sync register. You would create your own verilog block and use "import BVI" to import it into Bluespec... If you would be interested in this, I can post another example.... For customers using Eve/Zebu boxes there is a class of 2-1 and 1-2 sync fifos that take advantage of the aligned positive edges. But the compiler itself can't enforce the relative speed of the clocks if the clocks are brought in from outside the current module... But it will make sure they are not cross connected...

So becareful Smile

]import Clocks::*;

(* synthesize *)
module mkTest#(Clock c2, Reset r2)( );
Clock c1 <- exposeCurrentClock();
Reset r1 <- exposeCurrentReset();

Reg#(int) data1 <- mkReg(0, clocked_by c1, reset_by r1);
Reg#(int) tst1 <- mkSyncReg(0,c1,r1,c2);

Reg#(int) tst2 <- mkSyncReg(0,c2,r2,c1);

rule loadtst1;
tst1 <= data1;
endrule

rule loadtst2;
tst2 <= tst1;
endrule

endmodule

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Steve Allen
Senior Consulting Engineer
Bluespec, Inc
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hadar_agam



Joined: 10 May 2007
Posts: 38

PostPosted: Wed Jun 27, 2007 1:59 pm    Post subject: Reply with quote

Hello Eric,

If you know for sure that the two clocks are aligned, you have a few more options:

1. use mkNullCrossing synchronizers, but you will have to be very careful when moving data from the fast clock to the slow one (make sure not to lose data)

2. use the new attribute clock_family (will be documented in next release) above the module. This will specify that the two clocks are indeed from the same family, and the compiler will not ask for synchronization (again - take care of cases when crossing from 200Mhz to 100Mhz). the syntax is:

(* clock_family = "clk100, default_clock" *)
module mkTry#(Clock clk100, Reset rstn100M) (TRY_IFC);
.
.
.
endmodule

3. use mkSyncRegToSlow/mkSyncRegToFast synchronizers. You don't have to actually generate a divided clock - you only have to give a clock-divider interface to the synchronizers. See attached example.



specialMCD.bsv
 Description:
example of usage of mkSyncRegToSlow

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 Filename:  specialMCD.bsv
 Filesize:  1.65 KB
 Downloaded:  1891 Time(s)

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SteveA



Joined: 03 May 2007
Posts: 32

PostPosted: Fri Jun 29, 2007 2:14 pm    Post subject: Reply with quote

After a bit of tweaking for another project, I created a module called "DoubleReg.bsv" (attached).. the hides a bit of this implementation detail.. As always, it's good to create modules and use hierarchy where it makes sense.. This way you don't have to figure it out again... This double reg gets instantiated just like a normal register (with a few additions):


Reg#(int) regs <- mkDoubleRegFromCC(fastClock, fastResetN);

The trick is the _write method is called with clocks from the current clock domain, and the _read method is read from the clock domain supplied as parameters (fastClock, fastResetN) in this case...

I was lazy in two aspects here.. I always reset the registers to "unpack(0)" meaning hard 0, whatever that means... Could use "?" for no reset..

And, I left edge detection, etc, up to the caller... So clockReady is not even defined here.. Actually, it's not even needed by the registers themselves... It's just the routine you use to decide when the next cycle will be a rising edge of the slow clock Wink

But again, the point is to figure out what you need to do, then wrrap in into a module for later use (and reuse Wink



DoubleReg.bsv
 Description:

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 Filename:  DoubleReg.bsv
 Filesize:  756 Bytes
 Downloaded:  1932 Time(s)


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Steve Allen
Senior Consulting Engineer
Bluespec, Inc
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Wed Jul 04, 2007 12:31 pm    Post subject: thanks Reply with quote

Hadar, Steve,

Thanks for your examples. I managed to get going with the To- and From- registers.

Regards,
Eric
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kapilvar



Joined: 16 Apr 2008
Posts: 2

PostPosted: Fri Apr 18, 2008 7:58 am    Post subject: hi Reply with quote

these days i write the code for PS/2 keyboard interface in bluespec .....i m new in bluespec .....i am facing the problem of multiple clock ...any one can help me regarding this.....
actually i have to transfer the 8 bit of data one clock domain to the differnt clock domain ....
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