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Resets

 
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kirubi



Joined: 20 Oct 2009
Posts: 12

PostPosted: Thu Dec 24, 2009 11:51 pm    Post subject: Resets Reply with quote

Hello

Can anyone provide any examples for isResetAsserted? and isAsserted?

best
Venkat
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Dec 28, 2009 2:14 pm    Post subject: Re: Resets Reply with quote

I can give you an example of the syntax, but I've never used them before in a design so I can't give you an example of what you would use them for. They exists for when you need to write low-level code; you should rarely need to use it.

Is there something specific that you are trying to do? Or are you just reading through the manual and trying to understand everything?

The module "isResetAsserted" is, as I said, a module that you instantiate and it converts a BSV Reset into a BSV value. You would use isResetAssered in this way:
Code:
module mkMod (...);
   ReadOnly#(Bool) b <- isResetAsserted;
   // Or if you have a specific Reset called "rst":
   //let b <- isResetAsserted(reset_by rst);

   // Now you can refer to "b" anywhere
   rule r(b && ...);
      ...
   endrule

   ...
endmodule


The method "isAsserted" is part of the interface "MakeResetIfc" which is the interface of modules like "mkReset":
Code:
module mkMod(...);
   Clock clk <- mkAbsoluteClock(10,10);
   MakeResetIfc rst_ifc <- mkReset(2, True, clk);

   rule r (rst_ifc.isAsserted && ...);
      ...
   endrule
endmodule
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kirubi



Joined: 20 Oct 2009
Posts: 12

PostPosted: Mon Dec 28, 2009 10:04 pm    Post subject: Reply with quote

Thanks once again quark.

My idea is to use couple of reset signals that are generated inside and also provided from outside the module.

For example in certain scenarios you may want to trigger a reset based on the input reset and certain logic outcome inside the module.

Again this reset will be used within the modules for certain registers inside.

I am trying out various ways to do the above.

One of my goal is to get a bsv code equivalent to a hdl code and see if there are any differences in the generated verilog code of the bsc compiler.

I also have another question.. in case If I have reset(s) say insdl_rst generated inside I believe the methods cannot use them as they need to be available at the module boundary.

I can solve this error by declaring interface Reset rst_insd;inside the main interface ..and passing the value of insdl_rst to rst_inside after the rules are declared.

When compiled this adds a extra port rst_insd in .v file generated.

The issue however is I do-not want this rst_inside as verilog port.

Is there a way to do this?
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Dec 28, 2009 10:37 pm    Post subject: Reply with quote

If you do not export the reset in the interface, then BSC should only emit a warning and not a an error. So you should be able to leave the reset out of the interface and still be able to compile.

The warning is there because unexpected behavior can happen when a rule involves state that is reset by different signals; if some state is in reset and some is not, the rule might still fire but only update some of the state. But if you know that you are handling the rules and reset properly and you are sure that this situation will never happen, then you can ignore the warning.
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