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Multiple-clocks and ancestor_of attributes

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Joined: 20 Oct 2009
Posts: 12

PostPosted: Tue Dec 29, 2009 10:56 am    Post subject: Multiple-clocks and ancestor_of attributes Reply with quote


How do I go about doing this in blue-spec

I have two clocks say clk1khz and clk100khz which are inputs.clk1khz can be treated as default_clock and I have reset input reset_in

A counter is incremented based on clk1khz and when it reaches 999 it wraps around.

During this counting there are two values of count when count is 10'b0000000000 or count is 10'b0111110101 a gate enable- say clk1_enable is set for a clock clock1.

This clock1 is gated version of clk100khz.

I have a second clock clock2 which is gated version of clock1 and the gate condition is enabled by clk2_enable which is a sample of clk1_enable at clk100khz.

I have a third clock clock3 which is invertor of clock2.

Only clock3 must be an output from the module.

Rest of the clocks(clock1 and clock2) are generated and used internally.

What could be the best way to code the above in blue-spec?

More-specifically how do we use the ancestor_of_attributes.Is it necessary that all these must be available at the interface?

(If it must be so my basic requirement that the clocks generated inside must not appear as verilog ports get defeated.)

How do I check the value of count and issue an enable when count is incrementing based on certain count values.? Can I do that in a single rule? or Do I need to increment count in one rule and check the count value in another rule and get the enable? I could use two rules.My problem is passing the enable asserted in clock domain to another where it becomes a gate enable condition.

Also How do I pass the values of various enables from one clock domain to the above.

Can I use the same reset for all these enables/count etc?

Will this be reported as warning by blue-spec owing to same reset being used across clock domains(even though if they are gated version of the other)?

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