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Simulation of design

 
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nilay05



Joined: 21 Jul 2009
Posts: 10

PostPosted: Mon Aug 17, 2009 5:13 am    Post subject: Simulation of design Reply with quote

I am using bluespec GUI version. In that I am not able to simulate the design. I make changes in option window but still while simulating the design I am getting warnings and simulation is going on untill we press stop button. I am not able to understand where is the exact problem.
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hadar_agam



Joined: 10 May 2007
Posts: 38

PostPosted: Mon Aug 17, 2009 10:02 am    Post subject: simulation? Reply with quote

You mention that you are able to simulate the design until you press the stop button - why do you suspect it is not simulating?
Are you generating waveforms, or display statements?
What warnings are you getting?

If you want to stop a simulation in a controlled way, use the $finish() system task in your test-bench.

Information about $display, $finish, and other system tasks can be found in our user guide.
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nilay05



Joined: 21 Jul 2009
Posts: 10

PostPosted: Tue Aug 18, 2009 2:40 am    Post subject: Reply with quote

After simulation I am getting this warnings and only stop button is active ,rest of the butons are deactive.

vsim -do {run -all; quit} -lib work_mkOr -c -quiet -novopt main mkOr
# // ModelSim SE-64 6.3 May 4 2007 Linux 2.6.9-22.EL
# //
# // Copyright 1991-2007 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: mtech04 Hostname: malashri ProcessID: 14369
# Attempting to use alternate file "./wlftlOPf77".
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf. Using ./wlftlOPf77 instead.
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf. Using ./wlftlOPf77 instead.
# /cad/BlueSpec/Bluespec-2008.11.C/lib/Verilog/main.v(1Cool: [TFMPC] - Too few port connections. Expected 5, found 2.
# Region: :main:top
# ** Warning: (vsim-3722) /cad/BlueSpec/Bluespec-2008.11.C/lib/Verilog/main.v(1Cool: [TFMPC] - Missing connection for port 'oroutput_x_val'.
# ** Warning: (vsim-3722) /cad/BlueSpec/Bluespec-2008.11.C/lib/Verilog/main.v(1Cool: [TFMPC] - Missing connection for port 'oroutput_y_val'.
# ** Warning: (vsim-3722) /cad/BlueSpec/Bluespec-2008.11.C/lib/Verilog/main.v(1Cool: [TFMPC] - Missing connection for port 'read'.
# run -all
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Tue Aug 18, 2009 10:30 am    Post subject: Reply with quote

It looks like your similation executed, but there is no stimulus for the module, so nothing happens.

When you simulate a design with BSC, only a clock and reset are provided. No other ports are stimulated. So it is not useful to simulate a design which has an interface at the top-level. In this case, your module appears to have an "or" method of two inputs and a "read" method which returns the output.

You should probably write a testbench module, in BSC, which instantiates the module that you want to simulate, sends some inputs, gets back the results, prints the results with $display perhaps (or you can view the values in a VCD file), and then calls $finish to end the simulation. This can be done with rules or with the StmtFsm syntax.
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