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Unresetable data register in Verilog FIFO library

 
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wychen



Joined: 06 Nov 2007
Posts: 35

PostPosted: Fri Jul 11, 2008 8:22 pm    Post subject: Unresetable data register in Verilog FIFO library Reply with quote

A register not reset is a possible source of RTL/gate-level simulation mismatch. Whether a register should be reset is design dependent, and requires human analysis to determine that. Therefore, I think it is safer to reset all the registers by default, and change this behavior only in some cases where the designer can be sure that not resetting is desirable.

Whether the data registers in Verilog FIFO library are reset varies. In version 2007.08.B, it is reset by default, but after version 2008.01.A, it becomes not reset by default. This unexpected change caused some problems in my design, and it was non-trivial to pin down to this cause. As a result, these Verilog library should be examined to ensure all the registers are reset for safer ASIC flow (or also FPGA flow?). It would be convenient if this behavior is default, so it works out of box.

For those who want to implement ASIC designs, it is good to replace mkRegU by mkReg(?), unless you are sure it is harmless not to reset the register. If only RTL simulation is important, then it doesn't matter.
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SteveA



Joined: 03 May 2007
Posts: 32

PostPosted: Fri Jul 11, 2008 8:54 pm    Post subject: Reply with quote

I'm curious to hear more about the FIFO that gave you the reset problems. Guarded FIFOs should not be able to be read or written during reset anyway and you shouldn't be able to read data out of them no matter what state the registers actually are. By default, most of our registers actually come up initialized to AAAAAA, and reset sets them to 0 (unless you can specify otherwise, like with mkReg)..

I can imagine that unguarded FIFOs would be a bit more difficult since you might be depending on reading the data in the fifo without knowing if it was empty or full. This is a common design problem with any ASIC, and yes, you need to becareful of what gets reset and what doesn't...

But most projects treat power up and reset testing and a completely separate methodology and verification challenge. One doesn't normally reset *every* register by default because a reset register is more expensive than a non reset register. Thus it has been cosidered a waste of area to reset all registers in registerfiles, fifos, and similar banks of registers.

More immediately, you are always more than welcome to modify your library elements to reset everything by default. The files in lib/Verilog are the base files used, and adding addition reset logic is certainly within your abilities, though I would recommend making a copy of the library for your own use (and pointing to that library when running verilog and when synthesizing rather than the default library)...

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Steve Allen
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