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Synthesis boundary between BVI wrapper and the Verilog

 
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rasha



Joined: 25 Aug 2011
Posts: 14

PostPosted: Sun Apr 15, 2012 8:47 pm    Post subject: Synthesis boundary between BVI wrapper and the Verilog Reply with quote

Hello;

My general question is about FPGA/ASIC synthesis from Bluespec code.
Is there any preferred/suggested code structure/organization for facilitating this step?

In my specific case, this is what I'd like to do:

I want to write a "partial BVI wrapper". Let's say I have an UART, and I want to wrap only the "parallel side", so that it connects seamlessly to my Bluespec code. However, I want to leave the serial side (serialIn, serialOut) "exposed" in Verilog and accessible for routing constraint files.


(Note: I have matching "full BVI wrappers" for testing within BSV flow.)

Is something like this possible or is there a standard way this is done?
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