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Bluesim VCD dump is too slow.

 
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[email protected]



Joined: 31 May 2007
Posts: 4
Location: Austin. TX

PostPosted: Wed Jul 18, 2007 3:59 pm    Post subject: Bluesim VCD dump is too slow. Reply with quote

Hi,

For our debugging purposes, we are extensively depending on the dump.vcd files created by Bluesim/VCS. However, I observe a huge performance loss when I start dumping vcd: 9x to 14x increase in runtime. The penalty paid by turning dump on in VCS is much lower; less than 2x increase in runtime.

The runtimes are as below; all times are in seconds.
Code:
* bluesim -O3 dumpoff  :   9
* bluesim -O0 dumpoff  :  15
* vcs dumpoff          :  15
* bluesim -O3 dumpon   : 121 dumpsize=875M
* bluesim -O0 dumpon   : 135 dumpsize=875M
* vcs dumpon           :  27 dumpsize=1004M


(Here, -O3 and -O0 refer to the options passed to g++).

Is there anything we can do to speed up the dumping?

Thanks!
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Wed Jul 18, 2007 4:50 pm    Post subject: Bluesim VCD Speed Reply with quote

Hi, I am Jeff Newbern, an engineer at Bluespec developing the Bluesim simulator.

Would you be willing to send me a testcase which demonstrates the slow VCD dumping times? I can then profile it and work on performance optimizations for you.

Unfortunately, there is not much that you can do to influence the VCD dump performance externally.

VCD dumping is faster for an event-driven Verilog simulator, since the VCD format was developed for exactly that purpose. VCD dumping is more expensive for Bluesim because it is not based on an underlying event model that computes values at the same times as Verilog would. Therefore, Bluesim must sometimes retain values and meta-information across cycle boundaries so that it can reconstruct a VCD file that matches what Verilog would generate on the same input. I doubt that our VCD dumping speed will ever equal that of a Verilog simulator for which the VCD format was designed, but with performance optimization we may be able to get much closer than 4x to 5x!

Thank you,
Jeff Newbern
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[email protected]



Joined: 31 May 2007
Posts: 4
Location: Austin. TX

PostPosted: Thu Jul 19, 2007 11:37 am    Post subject: Reply with quote

I see.

Right now, it is a little complicated to send you a testcase. Actually, we are doing hardware/software codesign using Bluespec (simulated using BDPI), and I cannot send you the software portion (yet). In any case, we shall soon be developing a hardware-only design, which I will be able to send it over to you.

By the way, our design has over 300 rules (and we only (*synthesize*) the top module). Some of our modules make extensive use of RWires. A larger design does seem to affect the bsc compile speed a lot, but do you think this could also affect VCD dump performance?

Thanks!
nikhil
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Thu Jul 19, 2007 12:46 pm    Post subject: Reply with quote

Nikhil,

Don't worry about sending a testcase then. I am looking at VCD performance now based on other testcases we already have.

As for the synthesized module size affecting the VCD speed, it believe it can. I think it would not be affected as much as the bsc compile speed, but I would expect the VCD dumping speed to slow down more than linearly with the design size (something like O(n log n)).

Jeff
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