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Bluetcl module load command error

 
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vennsa



Joined: 15 Aug 2011
Posts: 5

PostPosted: Wed Aug 17, 2011 3:04 pm    Post subject: Bluetcl module load command error Reply with quote

Hi,

I've been trying to use the Bluetcl interface to access information about my compiled design (generated all the .bi/.bo/.ba files) and I get an error whenever I try to run a module load command like:
Code:

% package require Bluetcl
% Bluetcl::bpackage load DMA
% Bluetcl::module load DMA::mkDMA


The error I get is:
Code:

Error: Command line: (S0049)
  You must specify -sim or -verilog for linking.


"DMA::mkDMA" is listed by the "defs module" command for "DMA". The module loading doesn't accept the -sim or -verilog command. My compile command was:
Code:

bsc -u -verilog  -elab -keep-fires -keep-inlined-boundaries DMA.bsv


Basically, I was hoping to be able to write a script to automatically translate a signal in the generated verilog back into the locations its used/defined in the Bluespec source; however, I can't seem to load information about my synthesized module (I did remember the synthesize directive).

Any thoughts on what I'm doing wrong? Is there perhaps an easier to way to accomplish the backwards translation?
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Wed Aug 17, 2011 3:25 pm    Post subject: Re: Bluetcl module load command error Reply with quote

Before loading the module, try this:
Code:
% Bluetcl::flags set -verilog

The Bluetcl environment includes a record of the flags in use. This command will set the flag for the Verilog backend.
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vennsa



Joined: 15 Aug 2011
Posts: 5

PostPosted: Wed Aug 24, 2011 11:09 am    Post subject: Reply with quote

Thanks
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