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Possible to disable VPI wrappers?

 
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Thu Apr 07, 2011 4:33 pm    Post subject: Possible to disable VPI wrappers? Reply with quote

I'm using a variety of BDPI wrappers for C functions that are only meant to be compiled with Bluesim. When I run the Verilog backend, I get a bunch of VPI wrappers. Is there any way to disable the generation of VPI wrappers?

Thanks,
--Eric
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quark
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Joined: 02 Nov 2007
Posts: 495

PostPosted: Thu Apr 07, 2011 5:18 pm    Post subject: Reply with quote

Let me see if I understand: When generating Verilog, BSC generates wrapper files for imported foreign functions; these functions are not used in the Verilog design, and so the wrappers are never used during the Verilog linking step, but you'd like to prevent BSC from generating the extra files (to avoid clutter or to not to waste the time). Is that correct?

BSC has a two step process: compile and then link. For Verilog, the compile step generates the Verilog files and the link step just gathers up all the appropriate files and executes your Verilog simulator with the appropriate flags. But you can do this second step on your own, without calling BSC a second time. So BSC needs to be prepared for that situation.

As a result, BSC has to generate VPI wrapper files during compilation, because there may not be a link step (which would be a natural place to wait to generate the wrapper). During compilation, BSC doesn't yet know which import-BDPI functions will be used in the final design, so it has to generate wrappers for all of them.

BSC could have a flag to suppress generating wrappers during the compile step, but unfortunately it doesn't yet have such a flag.

So I can see two ways to solve your problem. One is to put the import-BDPI functions in a separate file and to use pre-processor macros to not import that file when compiling for Verilog. The pre-processor already defines __GENVERILOG__ when using the Verilog backend, so you could do something like this:
Code:
`ifndef __GENVERILOG__
import  BDPIFunctions::*;
`endif


An alternative is to set up your files so that the BDPIFunctions file is a library, in separate directories. You can compile it for Bluesim and Verilog off to the side, and then have your main code just import these files from that other location. This way, the generated wrapper files will sit off to the side, in a separate directory, apart from the files that get generated for the main design.

Do either of these help?
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Thu Apr 07, 2011 7:09 pm    Post subject: VPI Reply with quote

Thanks for the quick reply. Although clutter is a slight nuisance, the main issue is that we are utilizing a Verilog simulator from Xilinx (ISIM) that doesn't support VPI. As a result, there are various VPI system calls that have to be manually pruned from the Verilog to avoid errors with the simulator.

Some of the BDPI functions we are importing are purely for debugging purposes in Bluesim (e.g., printing a float value in C) but aren't needed in Verilog simulation.

The only solution I can think of for now (which is messy) is to locate every invocation of a BDPI function and to surround their calls using IFDEFs that check if the target is Verilog or Bluesim.
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quark
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Joined: 02 Nov 2007
Posts: 495

PostPosted: Sun May 08, 2011 12:25 am    Post subject: Re: VPI Reply with quote

Maybe I misunderstood. All you really care about is that you don't want the BDPI calls in the Verilog simulation -- whether the wrapper files are generated and exist in some directory is irrelevant, if they're not ever used in the Verilog simulation?

In that case, you don't need ifdef macros at all. Just use pure BSV to select between the BDPI function (when compiling for Bluesim) and a null Action (when compiling for Verilog). That will generate Verilog without the foreign function calls.

For example, if you had this:
Code:
import "BDPI" function myFunc ...;

module myMod();
   ...
   myFunc(...);
   ...
endmodule


Just wrap "myFunc" in an if-statement which replaces it with noAction when compiling for Verilog:

Code:
function myFunc2(...);
   if (genVerilog)
      return noAction;
   else
      return myFunc(...);
endfunction

module myMod();
   ...
   myFunc2(...);
   ...
endmodule
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