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Mistake both doc & compiler in BVI port

 
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test001
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PostPosted: Tue Jan 19, 2010 3:46 am    Post subject: Mistake both doc & compiler in BVI port Reply with quote

We can found follow code in document page 130.
But you will get compile error at port TM.
I think the compiler cann't support width as "1'b0".

Code:
Example - Setting port widths to a speci c width:
// Tie off the test ports
port TM = 1'b0 ; // This ties off the port TM to a 1 bit wide 0
Bit#(w) z = 0;
port TD = z ; // This ties off the port TD to w bit wide 0
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quark
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Joined: 02 Nov 2007
Posts: 496

PostPosted: Sun Jan 24, 2010 3:45 am    Post subject: Re: Mistake both doc & compiler in BVI port Reply with quote

Thank you for bringing this to our attention.

The syntax "1'b0" is equivalent to unpacking a Bit#(1) value into a value of another type. In this code, the other type is not mentioned -- it could be Bool, UInt#(1), Int#(1), etc. The error message indicates that the type is ambiguous.

We will fix the documentation and consider improving BSC to default the type to Bit#(1) in this situation.
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