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swrite bluesim bug

 
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patil.nikhil



Joined: 17 Aug 2007
Posts: 69
Location: University of Texas at Austin

PostPosted: Tue Dec 08, 2009 2:11 am    Post subject: swrite bluesim bug Reply with quote

Hi,

Here's a (minor) bug in the handling of swrite in bluesim.

(*synthesize*)
module mkA
();
rule r;
Bit#(64) x <- $swriteAV("12345678");
$display("%x", x);
$finish;
endrule
endmodule

With -sim, the output is: 000000003536373c
With -verilog -vsim nc, the output is: 3132333435363738

Thanks
nikhil
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jnewbern



Joined: 18 Jul 2007
Posts: 71

PostPosted: Tue Dec 08, 2009 11:53 am    Post subject: Reply with quote

Nikhil,

Thank you for the bug report. I was able to find and fix the bug quickly thanks to the simple testcase you provided. The fix will make it into the next release.

The bug only affects destinations greater than 32 bits in width. So you may be able to work around the problem by splitting the destination and using multiple $swriteAV tasks.

Regards,
Jeff
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