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modeling 2 write ports in Bluesim

 
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Wed Aug 22, 2007 5:37 am    Post subject: modeling 2 write ports in Bluesim Reply with quote

Hi all, I'm trying to make my entire design Bluesim-compatible, however I'm running into a problem. My design requires the use of 2-ported RAMs, with each individual port capable of a read or write on every cycle. So on 1 cycle, it could be possible to have 2 simultaneous writes. As far as I know, there aren't any memory structures (e.g., RegFile) that support this. I have been "faking" it so far by simply creating a vector of registers, but I'm certain this is not the most efficient way since my design utilizes a large number of such RAMs. I'm not certain if that is the cause, but my design in Bluesim runs at 2-4x slower than that of the generated Verilog simulated with VCS. Somehow, this doesn't seem right. I want to make sure that I'm using the right memories. Is there any workaround?

Thanks,
Eric
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ndave



Joined: 14 Aug 2007
Posts: 5

PostPosted: Wed Aug 22, 2007 10:32 am    Post subject: Re: modeling 2 write ports in Bluesim Reply with quote

I think the correct solution is to have a new regfile, but that's a tad painful.

Here's a suggestion though. 4 registerFiles, two containing data, and two containing Bits. Use the two Bool Regfiles to hold which is newer (with the Bools being different as meaning the first and the same as the second data regfile). Each regfile is written only once per cycle.

*When you read you read all four and select the correct value.
*When you write (port 1) you read two Bools and update the bit 1 and data 1 as appropriate.
*When you write (port 2) you read two Bools and update the bit 2 and data 2 as appropriate.

It may save you some time. But it will take more memory.

A better solution temporary solutoin may be a C Regfile
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eschung



Joined: 14 Jun 2007
Posts: 14

PostPosted: Wed Aug 20, 2008 12:32 am    Post subject: fixed BRAM code Reply with quote

I sincerely apologize to anyone who had trouble getting my piece of code to work. I am at a loss as to what I was thinking before. The old code absolutely makes no sense to me. Here is another go:

Code:

interface BRAM_2W_1R#(type index_t, type data_t);
  method Action write_0(index_t idx, data_t data);
  method Action write_1(index_t idx, data_t data);
  method Action read(index_t idx);
  method data_t value();
endinterface


module mkBRAM_2W_1R_sim (BRAM_2W_1R#(index_t, data_t))
                         provisos(Bits#(data_t, data_nt),
                                  Bits#(index_t, index_nt),
                                  Eq#(index_t),
                                  Literal#(index_t)
                                );

  Integer hi = 2**valueof(index_nt)-1;

  RegFile#(index_t, data_t)   arr_0    <- mkRegFileWCF(0, fromInteger(hi));
  RegFile#(index_t, data_t)   arr_1    <- mkRegFileWCF(0, fromInteger(hi));

  RegFile#(index_t, Bit#(1))  which_0  <- mkRegFileWCF(0, fromInteger(hi));
  RegFile#(index_t, Bit#(1))  which_1  <- mkRegFileWCF(0, fromInteger(hi));

  Reg#(data_t)                read_val <- mkReg(unpack(0));

  method Action write_0( index_t idx, data_t data );
    arr_0.upd(idx, data);
    case({which_1.sub(idx),which_0.sub(idx)})
      2'b01:  which_0.upd(idx, 0);
      2'b10:  which_0.upd(idx, 1);
    endcase
  endmethod

  method Action write_1( index_t idx, data_t data );
    arr_1.upd(idx, data);
    case({which_1.sub(idx),which_0.sub(idx)})
      2'b00:  which_1.upd(idx, 1);
      2'b11:  which_1.upd(idx, 0);
      default: noAction;
    endcase
  endmethod

  method Action read( index_t idx );
    action
      let v0 = arr_0.sub( idx );
      let v1 = arr_1.sub( idx );

      let w0 = which_0.sub( idx );
      let w1 = which_1.sub( idx );

      if(w0 == w1) read_val <= v0;
      else         read_val <= v1;
    endaction
  endmethod

  method data_t value();
    return read_val;
  endmethod

endmodule
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