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Simulating bluespec converted to verilog in QuestaSim

 
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sreeju



Joined: 31 Aug 2018
Posts: 5

PostPosted: Fri Sep 27, 2019 12:35 am    Post subject: Simulating bluespec converted to verilog in QuestaSim Reply with quote

I have slave design Bluespec which is converted into verilog and master design in traditional verilog.
As the slave interface has put interface in bsv the converted verilog intertface is :
input [7:0] d_in;
input EN_d_in;
output RDY_d_in;

In the Top file the connection are like:

d_out (master) -> d_in(slave)
RDY_d_out (master) -> EN_d_in(slave)
EN_d_out (master) <- RDY_d_in(slave)

while running this simulation,
master generated transaction on d_out channel with the RDY signal. As per the handshaking procedure slave should accept the data and EN signal on EN_d_in and generate the RDY signal as an acknowledge to the transaction but the slave accepting the transaction but not generating the RDY signal as acknowledge.
Is my understanding of handshaking is correct?
I am using the QuestaSim for simulation.
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quark
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Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Sep 30, 2019 2:04 pm    Post subject: Reply with quote

You cannot connect the Get and Put interfaces in this way. The protocol is: the RDY output indicates that the EN input may be asserted in the current clock cycle. In order to connect a Get and a Put, you must introduce an AND gate: you can't move data unless both interfaces indicate RDY. If one side is not RDY, you must not enable the other side. So you have to AND the RDY signals together and connect that to the EN inputs:

wire both_RDY = d_out$RDY && d_in$RDY;
EN_d_in <- both_RDY
EN_d_out <- both_RDY

If you want to connect the interfaces with only wires (without adding a gate), then you must change one side to use a different interface. As you mention, you can connect the two interfaces with wires if one side provides an ACK signal instead of a RDY signal. That side will contain the AND gate, checking its own RDY condition internally and returning the combination as the ACK signal. This is not what Get/Put implement, though.
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sreeju



Joined: 31 Aug 2018
Posts: 5

PostPosted: Tue Oct 01, 2019 7:06 am    Post subject: Reply with quote

I followed your suggestion of using the AND gate. But the master generates the RDY signal (d_out$RDY) but the slave is not generating the RDY (d_in$RDY)signal.
As the slave is bluespec generated verilog it should automatically generate RDY signal but it doesn't. All the clock and reset signals are given properly.
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quark
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Joined: 02 Nov 2007
Posts: 499

PostPosted: Tue Oct 01, 2019 9:12 am    Post subject: Reply with quote

Perhaps your design is never ready. Also, look for warnings during generation, as BSC can warn if a rule or method will never be ready because of scheduling conflicts. You can also look in the generated Verilog (which should be understandable) to follow how the RDY is defined and why it's not being asserted. (You can also add the "--keep-fires" flag to BSC to prevent BSC from inlining signals related to RDY/EN, which might make the Verilog slightly easier to follow.)
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quark
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Joined: 02 Nov 2007
Posts: 499

PostPosted: Tue Oct 01, 2019 9:20 am    Post subject: Reply with quote

You ought to be able to debug the problem by looking at waveforms and relating the Verilog signals back to the source design. There is document in the Bluespec release, doc/BSV/bsv-verification-guide.pdf, that has a chapter #7 "Observing Execution and Debugging BSV Blocks" that might help describe how to do this. The Bluespec Workstation GUI also has some features for automating the finding of related signals from the source, although some of that automation only works with certain waveform viewers.
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