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SyncFIFOCount strange behavior (bug?)

 
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tspalink



Joined: 05 Nov 2015
Posts: 12

PostPosted: Wed Apr 13, 2016 6:54 pm    Post subject: SyncFIFOCount strange behavior (bug?) Reply with quote

For simulation, I have the following code:

Code:
   SyncFIFOCountIfc#(step_pos, 2) fifo <- mkSyncFIFOCount(
      clock, reset, clock);

   Reg#(step_pos) pos <- mkReg(0);

   seq
      repeat (40)
      action
         $write("%d: level %d/%d (%b), not_full ", pos, fifo.sCount,
                fifo.dCount, fifo.dCount,
                fshow(fifo.sNotFull), ", not_empty ", fshow(fifo.dNotEmpty));
         if (fifo.dNotEmpty) $display(" ", fshow(fifo.first));
         else $display("");

         if (pos < 3) fifo.enq(pos);
         if (pos > 10 &&& pos < 13) fifo.deq();
         if (pos > 20 &&& pos < 23) fifo.enq(pos);
         if (pos > 30 &&& pos < 33) fifo.deq();

         pos <= pos + 1;
      endaction
   endseq;


which produces the following output, where cycle 32 is the most interesting:

Quote:
0: level 0/0 (00), not_full True, not_empty False
1: level 1/0 (00), not_full True, not_empty False
2: level 1/1 (01), not_full True, not_empty True 0
3: level 2/1 (01), not_full False, not_empty True 0
4: level 2/1 (01), not_full False, not_empty True 0
5: level 2/1 (01), not_full False, not_empty True 0
6: level 2/2 (10), not_full False, not_empty True 0
7: level 2/2 (10), not_full False, not_empty True 0
8: level 2/2 (10), not_full False, not_empty True 0
9: level 2/2 (10), not_full False, not_empty True 0
10: level 2/2 (10), not_full False, not_empty True 0
11: level 2/2 (10), not_full False, not_empty True 0
12: level 2/2 (10), not_full False, not_empty True 1
13: level 2/1 (01), not_full False, not_empty True 2
14: level 2/0 (00), not_full False, not_empty True 2
15: level 1/0 (00), not_full True, not_empty True 2
16: level 0/0 (00), not_full True, not_empty True 2
17: level 0/0 (00), not_full True, not_empty True 2
18: level 0/0 (00), not_full True, not_empty True 2
19: level 0/0 (00), not_full True, not_empty True 2
20: level 0/0 (00), not_full True, not_empty True 2
21: level 0/0 (00), not_full True, not_empty True 2
22: level 1/0 (00), not_full True, not_empty True 2
23: level 2/0 (00), not_full False, not_empty True 2
24: level 2/0 (00), not_full False, not_empty True 2
25: level 2/1 (01), not_full False, not_empty True 2
26: level 2/2 (10), not_full False, not_empty True 2
27: level 2/2 (10), not_full False, not_empty True 2
28: level 2/2 (10), not_full False, not_empty True 2
29: level 2/2 (10), not_full False, not_empty True 2
30: level 2/2 (10), not_full False, not_empty True 2
31: level 2/2 (10), not_full False, not_empty True 2
32: level 2/254 (11111110), not_full False, not_empty True 21
33: level 2/1 (01), not_full False, not_empty True 22
34: level 2/0 (00), not_full False, not_empty True 22
[STALL]


I find it fascinating that the $write decides on during cycle 32 that dCount is an 8 bit value, while on all other cycles it knows dCount only has 2 bits.

I have not dug into this in any depth yet, but a brief look at the Verilog implementation makes me wonder about a Gray code off-by one?
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stoy



Joined: 22 Aug 2007
Posts: 17
Location: Bluespec

PostPosted: Thu Apr 28, 2016 8:40 am    Post subject: Reply with quote

Yes, I regret to say that there is a bug in the Verilog primitive behind mkSyncFIFOCount (and mkSyncFIFOLevel), allowing the FIFO to accept one more "enq" than it has room for. Unfortunately the same bug occurs in the primitive for mkSyncFIFO, and also in the internal Bluesim models for the two primitives (so Bluesim gives the same wrong behaviour as a Verilog simulation). We apologise for this error, and shall fix it as soon as possible.

In the meantime, it might be worth noting that mkSyncBRAMFIFO does not have this bug, and can be used in place of mkSyncFIFO. (The crucial diffierence is that the Gray code manipulation for mkSyncBRAMFIFO is done in BSV, rather than in Verilog -- readers might wish to draw their own conclusions from the fact that the BSV version is correct, while the RTL one is not.)

Incidentally, the "fascinating" decision to output the count as an eight-bit value, rather than the correct two-bit size, is an extra Bluesim oddity, that does not occur in a Verilog simulation. We'll fix that too.

joe stoy
Bluespec Inc
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ewc



Joined: 08 May 2007
Posts: 31

PostPosted: Fri May 13, 2016 12:50 pm    Post subject: Reply with quote

The mkSyncFIFOLevel and mkSyncFIFO modules hold 1 more element than the fifoDepth parameter. This is to accommodate the output register which is necessary to meet timing requirements. Do note that the depth may be increased to the power of 2 +1 value.

It appears that the fifoCounts do not reflect the data held in the output registers. This looks like a bug.

I do not see any example of data loss in the example.

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Ed C
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