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Interfacing BSV with RTL in C

 
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tomahawkins



Joined: 14 Dec 2012
Posts: 21

PostPosted: Tue Feb 10, 2015 10:35 am    Post subject: Interfacing BSV with RTL in C Reply with quote

What's the best way to have a BSV testbench drive a gate-level C model while still providing the same interface as the original BSV design module?

In our case we have a design that provides a FIFO interface:

Code:

module mkSomething (FIFO#(Bit#(8)));
  ...
endmodule


In our flow, we use BVI to test a low level Verilog representation of the design. BVI makes this easy because it allows us to link each interface method with the associated data and control signals in the Verilog IO:

Code:

`ifdef VERILOG_BUILD

import "BVI"
module mkSomething (FIFO#(Bit#(8)));
  default_clock clk (CLK);
  default_reset rst (RST_N) clocked_by (clk);
  method enq (enq_1) enable (EN_enq) ready (RDY_enq);
  method deq () enable (EN_deq) ready (RDY_deq);
  method clear () enable (EN_clear) ready (RDY_clear);
  method first first () ready (RDY_first);
endmodule

`endif


However, the problem comes when we try to do the same thing with a C model using BDPI, since BDPI only import external C functions, it doesn't translate clocked IO signals into interface methods.

What is the best way to call the imported C functions below and still retain the FIFO interface and achieve a cycle equivalent simulation?

(Unfortunately we have to use C, not Verilog, for reasons not mentioned).

Code:

`ifdef C_BUILD

import "BDPI" function Action init;  // Init the C model.
import "BDPI" function Action step;  // Step the C model (i.e. clock it).
import "BDPI" function Action set_EN_enq (Bool en);  // Set the enq EN input.
import "BDPI" function Action set_enq_1(Bit#(8) a);  // Set the enq data.
import "BDPI" function Bool get_RDY_enq;  // Get the enq RDY output.
...
module mkSomething (FIFO#(Bit#(8)));
  // How to call BDPI functions to preserve cycle accuracy with original BSV module?
endmodule

`endif


-Tom
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 500

PostPosted: Tue Feb 10, 2015 3:47 pm    Post subject: Re: Interfacing BSV with RTL in C Reply with quote

My first thought is to declare a BSV module for "mkSomething" which will have methods that write directly to wires. These wires can capture both the EN and the data for the methods. Then, in a rule inside "mkSomething", you would call the BDPI functions to set the values according to the wires; and you would call BDPI functions to read values, to set on outgoing wires; and then you would call the step function. (If you need to decouple the read and write sides, for scheduling, you might be able to use two separate rules.) For the init function, you could declare a Reg#(Bool) called "initialized" that starts as False; have an action that sets it to True and calls the BPDI init functions. To guarantee that this action happens first, it could be done as the first step of the single rule in the module; or, it could be done in a separate rule, and every other method and rule could have "initialized" as part of their explicit condition (to make sure that the module doesn't respond until it's initialized).

Does something like that work? Alternatively, some Verilog simulators support co-sim, in which case the BSV could still use import-BVI and the third-party simulator would be responsible for stitching things together -- if you have a simulator that supports that.
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quark
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Joined: 02 Nov 2007
Posts: 500

PostPosted: Tue Feb 10, 2015 3:51 pm    Post subject: Re: Interfacing BSV with RTL in C Reply with quote

Another option might be to run the DUT on a gated clock, while still having an ungated clock for doing model bookkeeping. In effect, emulating the DUT rather than running it directly. The gated clock could be run at half speed and the BDPI calls could run on the ungated clock, on the off cycles.
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jamey



Joined: 15 Jan 2008
Posts: 5

PostPosted: Wed Sep 02, 2015 11:03 am    Post subject: Reply with quote

In case you did not find a way to do this, we have a module like this that might be a helpful example:

https://github.com/cambridgehackers/connectal/blob/master/bsv/SimDma.bsv
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