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synthesize attribute that flattens sub-modules

 
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3pitom3



Joined: 24 Sep 2013
Posts: 3

PostPosted: Thu Jul 02, 2015 9:53 am    Post subject: synthesize attribute that flattens sub-modules Reply with quote

Is there a version of the (*synthesize*) that flattens the sub-modules of a top-level module even if they have their own (*synthesized*) attribute?

For example, if I have a top module top, and three sub-modules a, b, c, and if I put (*synthesize*) next to each one, that will create 4 verilog files: top.v, a.v, b.v, c.v.

Now top.v will have a, b, c instantiated as modules, but I would like it to be a flattened netlist.

What I can do to work around the issue is compile once with the attributes above, then remove the (*synthesize*) for a, b, c, and recompile to get the flattened top.

However, this is slower, since it modifies the BSV source and makes the compiler regenerate each of the modules, whereas it has just done that work, and it would be good to be able to re-use it.
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Thu Jul 02, 2015 11:17 am    Post subject: Re: synthesize attribute that flattens sub-modules Reply with quote

No, there is no such attribute. If you want to synthesize a design as one module but also have BSC produce separate copies of the submodules, then you can define new modules for those and put "synthesize" on those. For example:
Code:
module mkA(A_Ifc);
   ... implementation ...
endmodule

// create an alias for mkA and synthesize it
(* synthesize *)
module mkA_synth(A_Ifc);
   let _ifc <- mkA;
   return _ifc;
endmodule

// top-level design uses the original mkA and not the copies
(* synthesize *)
module mkTop(Top_Ifc);
   A_Ifc a <- mkA;  // not separately synthesized
   ...
endmodule
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3pitom3



Joined: 24 Sep 2013
Posts: 3

PostPosted: Thu Jul 02, 2015 11:58 am    Post subject: Reply with quote

Ah yes that makes sense, thanks!
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