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bluespec vs verilog design

 
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hyteo



Joined: 30 Sep 2014
Posts: 3

PostPosted: Mon Apr 20, 2015 10:02 am    Post subject: bluespec vs verilog design Reply with quote

HI,

I'm noticed one of the signals in my bluespec design was delayed by one cycle. After I compiled the design to verilog and simulated it using modelsim. The one cycle latency was removed. May I know whether is there any differences in cycle time between bluespec and verilog design? Do you expect this kind of behavior?

Thanks
Yap
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Apr 20, 2015 1:22 pm    Post subject: Re: bluespec vs verilog design Reply with quote

There should be no differences between Bluesim simulation and Verilog simulation. If you observe a cycle delay, that is a bug. Can you provide the design, so that we can have a look?
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ShepSiegel



Joined: 14 Aug 2007
Posts: 41

PostPosted: Mon Apr 20, 2015 5:21 pm    Post subject: Reply with quote

FWIW to the OP, we've been using Bluesim for the better part of a decade and except for the well-documented behavior with non-synthesizable directives like $display, Bluesim is bit and cycle true to the RTL.
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hyteo



Joined: 30 Sep 2014
Posts: 3

PostPosted: Sun May 03, 2015 8:44 am    Post subject: Reply with quote

HI,

I did some changes on my bluespec design.
Both Verilog and Bluesim simulations are now the same.

Thanks Very Happy
HY
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