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Buggy SizedFIFO when using Xilinx XST and BlockRAM

 
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oarcas



Joined: 24 Feb 2011
Posts: 9

PostPosted: Sun Dec 21, 2014 9:18 am    Post subject: Buggy SizedFIFO when using Xilinx XST and BlockRAM Reply with quote

Hi,

I wanted to raise attention about SizedFIFOs as BlockRAMs in Xilinx FPGAs. This topic was addressed in another post (http://bluespec.com/forum/viewtopic.php?t=97), also mentioning the limitations of Xilinx XST when inferring RAMs.

In this case, I realized that when I implement SizedFIFOs and XST (14.4) decides that the RAM should be implemented as a BlockRAM (using an internal threshold, it seems), the generated hardware exhibits erratic and random behavior. Specifically, I noticed random transitions of the notFull and notEmpty signals.

I don't know if somebody previously posted about this.

These problems seem to not happen using distributed RAM, or LUTRAM, which for small SizedFIFOs are not expensive. I implemented a mkFFSizedFIFO module which instantiates a copy of the SizedFIFO.v Verilog module, called FFSizedFIFO.v. In my version of SizedFIFO, I force the RAM to be distributed RAM using the following Xilinx attribute:

Code:
(* RAM_STYLE = "distributed" *)
reg [p1width - 1 : 0]     arr[0: p2depth2];


It took me a while to realize what was happening, because in 99% of the cases the error is mine, not because Xilinx generates buggy hardware Sad

The BSV code:

Code:
import FIFO::*;
import FIFOF::*;

import "BVI" FFSizedFIFO =
module mkFFSizedFIFO#(Integer n)(FIFO#(element_type))
        provisos(Bits#(element_type, width_any));
    default_clock clk(CLK);
    default_reset rst(RST);
   
    parameter               p1width = valueOf(width_any); // data width
    parameter               p2depth = n;
    parameter               p3cntr_width = log2(n - 1); // log(p2depth-1)
    // The -1 is allowed since this model has a fast output register
    parameter               guarded = 1;

    method enq(D_IN) enable(ENQ) ready(FULL_N);
    method D_OUT first() ready(EMPTY_N);
    method deq() enable(DEQ) ready(EMPTY_N);
    method clear() enable(CLR);
   
    schedule enq C enq;
    schedule enq CF first;
    schedule enq CF deq;
    schedule enq SB clear;

    schedule first CF first;
    schedule first SB deq;
    schedule first SB clear;

    schedule deq C deq;
    schedule deq SB clear;

    schedule clear SBR clear;
endmodule

import "BVI" FFSizedFIFO =
module mkFFSizedFIFOF#(Integer n)(FIFOF#(element_type))
        provisos(Bits#(element_type, width_any));
    default_clock clk(CLK);
    default_reset rst(RST);
   
    parameter               p1width = valueOf(width_any); // data width
    parameter               p2depth = n;
    parameter               p3cntr_width = log2(n - 1); // log(p2depth-1)
    // The -1 is allowed since this model has a fast output register
    parameter               guarded = 1;

    method enq(D_IN) enable(ENQ) ready(FULL_N);
    method FULL_N notFull();
    method D_OUT first() ready(EMPTY_N);
    method deq() enable(DEQ) ready(EMPTY_N);
    method EMPTY_N notEmpty();
    method clear() enable(CLR);
   
    schedule enq C enq;
    schedule enq CF first;
    schedule enq CF deq;
    schedule enq SB clear;

    schedule first CF first;
    schedule first SB deq;
    schedule first SB clear;

    schedule deq C deq;
    schedule deq SB clear;

    schedule clear SBR clear;
   
    schedule notFull SB enq;
    schedule notFull CF notFull;
    schedule notFull CF first;
    schedule notFull SB deq;
    schedule notFull CF notEmpty;
    schedule notFull SB clear;

    schedule notEmpty SB enq;
    schedule notEmpty CF first;
    schedule notEmpty SB deq;
    schedule notEmpty CF notEmpty;
    schedule notEmpty SB clear;
endmodule


And the changes necessary for the FFSizedFIFO (using the BSV 2014.07.A SizedFIFO.v original source):

Code:
--- a/SizedFIFO.v   2014-07-30 21:57:12.000000000 +0200
+++ b/FFSizedFIFO.v   2014-12-21 11:39:44.529509646 +0100
@@ -55,7 +55,7 @@
 
 
 // Sized fifo.  Model has output register which improves timing
-module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
+module FFSizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
    parameter               p1width = 1; // data width
    parameter               p2depth = 3;
    parameter               p3cntr_width = 1; // log(p2depth-1)
@@ -85,6 +85,7 @@
 
    // if the depth is too small, don't create an ill-sized array;
    // instead, make a 1-sized array and let the initial block report an error
+   (* RAM_STYLE = "distributed" *)
    reg [p1width - 1 : 0]     arr[0: p2depth2];
 
    reg [p1width - 1 : 0]     D_OUT;


Oriol
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Dec 22, 2014 12:53 pm    Post subject: Re: Buggy SizedFIFO when using Xilinx XST and BlockRAM Reply with quote

Hi Oriol,

We experienced several bugs with version 14.5, which Xilinx acknowledged as valid and said that the workaround was to upgrade to 14.6 (or higher).

I do not know if any Bluespec users have experienced problems with 14.4, but you might consider upgrading to 14.6 or later. I believe that we are currently using 14.7.

In any case, thank you for this report!
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 499

PostPosted: Mon Dec 22, 2014 1:01 pm    Post subject: Re: Buggy SizedFIFO when using Xilinx XST and BlockRAM Reply with quote

Sorry, I spoke too soon. I see now that someone reported a BRAM inference issue with 14.4 (aka 2012.4) back in early 2013. At the time, they decided to revert to 14.3. My recommendation would be to upgrade to 14.6 or 14.7 (or otherwise down to 14.3) and see if the original design works without the attribute.
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ShepSiegel



Joined: 14 Aug 2007
Posts: 41

PostPosted: Mon Dec 22, 2014 3:37 pm    Post subject: Reply with quote

This issue is dear to us, but only with current versions of the FPGA vendor's back-end tools. If you are seeing this with say, Vivado 2014.4, we would be interested in helping to resolve.
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oarcas



Joined: 24 Feb 2011
Posts: 9

PostPosted: Wed Dec 31, 2014 10:14 am    Post subject: Reply with quote

I am porting the design to a Virtex 7 with Vivado 2014.4. I'll check if the issue persists.

BTW, I found a BSV source in BLUESPEC_DIR/Verilog.Vivado/SizedFIFO.v with the same modification I described in my first post:

Code:
   (* RAM_STYLE = "DISTRIBUTED" *)
   reg [p1width - 1 : 0]     arr[0: p2depth2];


So it seems the solution was already shipped with BSV 2014.07.A.

Oriol
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