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Command line for compiling to verilog simulation with BDPI

 
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asutherland



Joined: 16 Dec 2013
Posts: 4

PostPosted: Tue Sep 23, 2014 4:48 pm    Post subject: Command line for compiling to verilog simulation with BDPI Reply with quote

I'm looking to find the correct command line to compile / link a design using BDPI for simulation with iverilog. The design simulates fine in bsim.

I have been trying variations on:

bsc -verilog -vsim iverilog -vsearch $(BLUESPECDIR)/VPI -e mkTestBench build/driver.v build/mkTestBench.v build/mkTop.v code.c build/bsc/read_pixel.ba build/bsc/write_pixel.ba build/vpi_wrapper_read_pixel.c build/vpi_wrapper_write_pixel.c

code.c contains two functions: read_pixel and write_pixel, driver.v provides top level clock signals.

The bsc generated files live in subdirectories build/ and build/bsc and I am not clear if I should use the -vsearch for the *.c and *.ba files. Also not clear how to set include path for *.h.

I am unsure what to do with the contents of $(BLUESPECDIR)/VPI which duplicates vpi_user.h that is installed by iverilog and provides libbdpi.so

A pointer to a fully worked example would be really helpful.

Thanks,
Andrew
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 495

PostPosted: Wed Sep 24, 2014 2:22 pm    Post subject: Re: Command line for compiling to verilog simulation with BD Reply with quote

You don't need the -vsearch flag. If it's working for Bluesim, then you can use the exact same command-line for Verilog by replacing -sim with -verilog and adding -elab. If you have multiple Verilog simulators on your system, then you will need to -vsim flag to specify which to use, but if you only have iverilog, then you don't need that flag either. Like this:
Code:
# bsc -verilog -elab -u TopFile.bsv
# bsc -verilog -e mkTopMod code.c

The -elab flag tells BSC to generate .ba files for each module in the hierarchy. When you compile for Bluesim, this flag is always on, because the .ba files will be needed for the linking step. When you call "bsc -sim -e mkTopMod" to link the modules into a simulation, you do not need to specify any .ba files on the command line. All you need to specify is the name of the top module, and BSC will look for "mkTopMod.ba" in the path. This file will contain the names of the submodules, and BSC will go looking for the .ba files for those submodules. In this way, BSC can follow the hierarchy and find all of the .ba files for all of the modules. This includes any .ba files generated for imported C functions.

In the past, when compiling for Verilog, BSC did not support generating .ba file. BSC would only generate .v files. The "bsc -verilog -e mkTopMod" linking step was unable to find the hierarchy (because it doesn't parser Verilog files), so you as the user had to list every Verilog file on the command line. BSC would still generate .ba files for imported C functions. So you also needed to list those .ba files on the command line.

BSC still supports that compile/link style for Verilog, for backwards compatibility. But now, things are easier. You can add the -elab flag to the compile step, to tell BSC to generate .ba files. And then the "bsc -verilog -e mkTopMod" step does not need any Verilog or .ba files to be specified on the command line. BSC will find that information by following the .ba hierarchy.

However, you still need to provide the implementation for the imported C function. There are several ways to do this. You can provide a C source file on the command line -- as I've shown above in the example, with "code.c". If you do this, BSC will compile the C file for you. However, you could have compiled the file yourself and provided the C object file "code.o" on the command-line instead. Or, if the imported function exists in a library somewhere, you can provide that library on the command line, or you can specify -L and -l flags for the C linker to include the library.

Finally, it may be worth knowing that when you run the BSC link step for Verilog, most of the work is done by a script that BSC calls. In the $BLUESPECDIR/bin/ directory, there are files called "bsc_build_vsim_*" for each of the known simulators. When you specify "-vsim simname", this causes BSC to go look for the script "bsc_build_vsim_simname". Inside this script are the steps for constructing the VPI files needed for each simulator and providing the appropriate flags to the Verilog simulator to create a simulation executable. So this script will take care of finding the VPI files that it needs. You shouldn't need to add $BLUESPECDIR/VPI/ to the vsearch path.
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asutherland



Joined: 16 Dec 2013
Posts: 4

PostPosted: Wed Sep 24, 2014 6:37 pm    Post subject: That works Reply with quote

Thank you that works.

For completeness I had to add:
-p .:../../common/ to handle all my source paths

and to get the intermediate files into the build dir.

-bdir build
-simdir build
-vdir build

and for the iverilog output

-o build/sim.out

There is a problem with the generated vpi wrapper which I will post in a new thread...
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