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Import BVI wizard error on read verilog

 
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garethlloyd



Joined: 19 Mar 2014
Posts: 12

PostPosted: Fri Aug 22, 2014 11:11 am    Post subject: Import BVI wizard error on read verilog Reply with quote

Code:
invalid command name "31:0"
invalid command name "31:0"
    while executing
"31:0"
    invoked from within
"bindtags .bvi.frame.vfr.vofr.votab.canvas.notebook.cs.page2.cs.input_fr.lwchildsite.clipper.canvas.sfchildsite.vi_[31:0]DLMB_readdbus_fr_0"
    (while creating component "vi_[31:0]DLMB_readdbus_fr_0" for widget "::.bvi")
    (object "::.bvi" method "::itk::Archetype::itk_component" )
    invoked from within
"itk_component add $name {
                frame $f.$name -takefocus 0
        }"
    (object "::.bvi" method "::import_bvi_wizard::add_frame" body line 2)
    invoked from within
"add_frame $f vi_$name\_fr_$id"
    (object "::.bvi" method "::import_bvi_wizard::add_verilog_input_field" body line 7)
    invoked from within
"add_verilog_input_field [lindex $i 0] "" ""  [lindex $i 1]"
    (object "::.bvi" method "::import_bvi_wizard::fill_param_input_output" body line 10)
    invoked from within
"fill_param_input_output $verilog_module_name $verilog_inputs  $verilog_outputs $verilog_parameters $verilog_inouts"
    (object "::.bvi" method "::import_bvi_wizard::find_param_input_output" body line 59)
    invoked from within
"find_param_input_output $cmds"
    (object "::.bvi" method "::import_bvi_wizard::read_verilog" body line 21)
    invoked from within
"read_verilog $f"
    (object "::.bvi" method "::import_bvi_wizard::open_verilog" body line 7)
    invoked from within
"::.bvi open_verilog 1"
    invoked from within
".bvi.frame.vfr.vbfr.open_verilog invoke"
    ("uplevel" body line 1)
    invoked from within
"uplevel #0 [list $w invoke]"
    (procedure "tk::ButtonUp" line 22)
    invoked from within
"tk::ButtonUp .bvi.frame.vfr.vbfr.open_verilog"
    (command bound to event)
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 496

PostPosted: Fri Aug 22, 2014 2:03 pm    Post subject: Re: Import BVI wizard error on read verilog Reply with quote

Thank you for reporting this bug. I would like to try to replicate the problem here, but I don't have the Verilog file. The error message points to the name "vi_[31:0]DLMB_readdbus_fr_0" -- are there ports by these names in your Verilog and do they use unusual syntax? I'm guessing that the bit range was unexpected by our Verilog parser.
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garethlloyd



Joined: 19 Mar 2014
Posts: 12

PostPosted: Sat Aug 23, 2014 7:10 am    Post subject: Reply with quote

The Verilog is straight out of Xilinx tools. I'm guessing the parse error is because Xilinx don't use any whitespace before the names.

Code:
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr  4 14:00:25 MDT 2014
//Date        : Thu Aug 21 14:09:13 2014
//Host        : mason running 64-bit Debian GNU/Linux 6.0.9 (squeeze)
//Command     : generate_target subtile_mb_subsystem_wrapper.bd
//Design      : subtile_mb_subsystem_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module subtile_mb_subsystem_wrapper
   (Clk,
    DLMB_abus,
    DLMB_addrstrobe,
    DLMB_be,
    DLMB_ce,
    DLMB_readdbus,
    DLMB_readstrobe,
    DLMB_ready,
    DLMB_ue,
    DLMB_wait,
    DLMB_writedbus,
    DLMB_writestrobe,
    ILMB_abus,
    ILMB_addrstrobe,
    ILMB_ce,
    ILMB_readdbus,
    ILMB_readstrobe,
    ILMB_ready,
    ILMB_ue,
    ILMB_wait,
    INTERRUPT_ack,
    INTERRUPT_address,
    INTERRUPT_interrupt,
    M0_AXIS_tdata,
    M0_AXIS_tlast,
    M0_AXIS_tready,
    M0_AXIS_tvalid,
    M1_AXIS_tdata,
    M1_AXIS_tlast,
    M1_AXIS_tready,
    M1_AXIS_tvalid,
    S0_AXIS_tdata,
    S0_AXIS_tlast,
    S0_AXIS_tready,
    S0_AXIS_tvalid,
    S1_AXIS_tdata,
    S1_AXIS_tlast,
    S1_AXIS_tready,
    S1_AXIS_tvalid,
    S_AXI_araddr,
    S_AXI_arready,
    S_AXI_arvalid,
    S_AXI_awaddr,
    S_AXI_awready,
    S_AXI_awvalid,
    S_AXI_bready,
    S_AXI_bresp,
    S_AXI_bvalid,
    S_AXI_rdata,
    S_AXI_rready,
    S_AXI_rresp,
    S_AXI_rvalid,
    S_AXI_wdata,
    S_AXI_wready,
    S_AXI_wstrb,
    S_AXI_wvalid,
    resetn);
  input Clk;
  output [31:0]DLMB_abus;
  output DLMB_addrstrobe;
  output [3:0]DLMB_be;
  input DLMB_ce;
  input [31:0]DLMB_readdbus;
  output DLMB_readstrobe;
  input DLMB_ready;
  input DLMB_ue;
  input DLMB_wait;
  output [31:0]DLMB_writedbus;
  output DLMB_writestrobe;
  output [31:0]ILMB_abus;
  output ILMB_addrstrobe;
  input ILMB_ce;
  input [31:0]ILMB_readdbus;
  output ILMB_readstrobe;
  input ILMB_ready;
  input ILMB_ue;
  input ILMB_wait;
  output [1:0]INTERRUPT_ack;
  input [31:0]INTERRUPT_address;
  input INTERRUPT_interrupt;
  output [31:0]M0_AXIS_tdata;
  output M0_AXIS_tlast;
  input M0_AXIS_tready;
  output M0_AXIS_tvalid;
  output [31:0]M1_AXIS_tdata;
  output M1_AXIS_tlast;
  input M1_AXIS_tready;
  output M1_AXIS_tvalid;
  input S0_AXIS_tdata;
  input S0_AXIS_tlast;
  output S0_AXIS_tready;
  input S0_AXIS_tvalid;
  input S1_AXIS_tdata;
  input S1_AXIS_tlast;
  output S1_AXIS_tready;
  input S1_AXIS_tvalid;
  input S_AXI_araddr;
  output S_AXI_arready;
  input S_AXI_arvalid;
  input S_AXI_awaddr;
  output S_AXI_awready;
  input S_AXI_awvalid;
  input S_AXI_bready;
  output [1:0]S_AXI_bresp;
  output S_AXI_bvalid;
  output [31:0]S_AXI_rdata;
  input S_AXI_rready;
  output [1:0]S_AXI_rresp;
  output S_AXI_rvalid;
  input S_AXI_wdata;
  output S_AXI_wready;
  input S_AXI_wstrb;
  input S_AXI_wvalid;
  input resetn;

  wire Clk;
  wire [31:0]DLMB_abus;
  wire DLMB_addrstrobe;
  wire [3:0]DLMB_be;
  wire DLMB_ce;
  wire [31:0]DLMB_readdbus;
  wire DLMB_readstrobe;
  wire DLMB_ready;
  wire DLMB_ue;
  wire DLMB_wait;
  wire [31:0]DLMB_writedbus;
  wire DLMB_writestrobe;
  wire [31:0]ILMB_abus;
  wire ILMB_addrstrobe;
  wire ILMB_ce;
  wire [31:0]ILMB_readdbus;
  wire ILMB_readstrobe;
  wire ILMB_ready;
  wire ILMB_ue;
  wire ILMB_wait;
  wire [1:0]INTERRUPT_ack;
  wire [31:0]INTERRUPT_address;
  wire INTERRUPT_interrupt;
  wire [31:0]M0_AXIS_tdata;
  wire M0_AXIS_tlast;
  wire M0_AXIS_tready;
  wire M0_AXIS_tvalid;
  wire [31:0]M1_AXIS_tdata;
  wire M1_AXIS_tlast;
  wire M1_AXIS_tready;
  wire M1_AXIS_tvalid;
  wire S0_AXIS_tdata;
  wire S0_AXIS_tlast;
  wire S0_AXIS_tready;
  wire S0_AXIS_tvalid;
  wire S1_AXIS_tdata;
  wire S1_AXIS_tlast;
  wire S1_AXIS_tready;
  wire S1_AXIS_tvalid;
  wire S_AXI_araddr;
  wire S_AXI_arready;
  wire S_AXI_arvalid;
  wire S_AXI_awaddr;
  wire S_AXI_awready;
  wire S_AXI_awvalid;
  wire S_AXI_bready;
  wire [1:0]S_AXI_bresp;
  wire S_AXI_bvalid;
  wire [31:0]S_AXI_rdata;
  wire S_AXI_rready;
  wire [1:0]S_AXI_rresp;
  wire S_AXI_rvalid;
  wire S_AXI_wdata;
  wire S_AXI_wready;
  wire S_AXI_wstrb;
  wire S_AXI_wvalid;
  wire resetn;

subtile_mb_subsystem subtile_mb_subsystem_i
       (.Clk(Clk),
        .DLMB_abus(DLMB_abus),
        .DLMB_addrstrobe(DLMB_addrstrobe),
        .DLMB_be(DLMB_be),
        .DLMB_ce(DLMB_ce),
        .DLMB_readdbus(DLMB_readdbus),
        .DLMB_readstrobe(DLMB_readstrobe),
        .DLMB_ready(DLMB_ready),
        .DLMB_ue(DLMB_ue),
        .DLMB_wait(DLMB_wait),
        .DLMB_writedbus(DLMB_writedbus),
        .DLMB_writestrobe(DLMB_writestrobe),
        .ILMB_abus(ILMB_abus),
        .ILMB_addrstrobe(ILMB_addrstrobe),
        .ILMB_ce(ILMB_ce),
        .ILMB_readdbus(ILMB_readdbus),
        .ILMB_readstrobe(ILMB_readstrobe),
        .ILMB_ready(ILMB_ready),
        .ILMB_ue(ILMB_ue),
        .ILMB_wait(ILMB_wait),
        .INTERRUPT_ack(INTERRUPT_ack),
        .INTERRUPT_address(INTERRUPT_address),
        .INTERRUPT_interrupt(INTERRUPT_interrupt),
        .M0_AXIS_tdata(M0_AXIS_tdata),
        .M0_AXIS_tlast(M0_AXIS_tlast),
        .M0_AXIS_tready(M0_AXIS_tready),
        .M0_AXIS_tvalid(M0_AXIS_tvalid),
        .M1_AXIS_tdata(M1_AXIS_tdata),
        .M1_AXIS_tlast(M1_AXIS_tlast),
        .M1_AXIS_tready(M1_AXIS_tready),
        .M1_AXIS_tvalid(M1_AXIS_tvalid),
        .S0_AXIS_tdata(S0_AXIS_tdata),
        .S0_AXIS_tlast(S0_AXIS_tlast),
        .S0_AXIS_tready(S0_AXIS_tready),
        .S0_AXIS_tvalid(S0_AXIS_tvalid),
        .S1_AXIS_tdata(S1_AXIS_tdata),
        .S1_AXIS_tlast(S1_AXIS_tlast),
        .S1_AXIS_tready(S1_AXIS_tready),
        .S1_AXIS_tvalid(S1_AXIS_tvalid),
        .S_AXI_araddr(S_AXI_araddr),
        .S_AXI_arready(S_AXI_arready),
        .S_AXI_arvalid(S_AXI_arvalid),
        .S_AXI_awaddr(S_AXI_awaddr),
        .S_AXI_awready(S_AXI_awready),
        .S_AXI_awvalid(S_AXI_awvalid),
        .S_AXI_bready(S_AXI_bready),
        .S_AXI_bresp(S_AXI_bresp),
        .S_AXI_bvalid(S_AXI_bvalid),
        .S_AXI_rdata(S_AXI_rdata),
        .S_AXI_rready(S_AXI_rready),
        .S_AXI_rresp(S_AXI_rresp),
        .S_AXI_rvalid(S_AXI_rvalid),
        .S_AXI_wdata(S_AXI_wdata),
        .S_AXI_wready(S_AXI_wready),
        .S_AXI_wstrb(S_AXI_wstrb),
        .S_AXI_wvalid(S_AXI_wvalid),
        .resetn(resetn));
endmodule
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 496

PostPosted: Tue Aug 26, 2014 1:24 pm    Post subject: Reply with quote

Ah, yes. The parser is expecting whitespace between the range and the name. We will fix that, thanks!

If you want to fix it locally, you can edit the file ${BLUESPECDIR}/tcllib/workstation/import_bvi_wizard_analysis.tcl, and go to the function "find_param_input_output", and below the comment "parse bit range" are two regexp commands that include "\s+" (which matches 1 or more whitespace characters). Those should be changed to "\s*", which will also match 0 whitespace characters.
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