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Limiting variable name length.

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Joined: 14 Dec 2012
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PostPosted: Thu May 29, 2014 11:19 pm    Post subject: Limiting variable name length. Reply with quote

We are using some Verilog tools that have a hard time reasoning about long variable names (I know, what decade is this?). Is there a compiler switch to limit name length?


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PostPosted: Sun Jun 01, 2014 4:01 pm    Post subject: Re: Limiting variable name length. Reply with quote

There is not a flag like this, although it is something that we could add. You could also consider using the -verilog-filter flag to specify a script to run on the generated Verilog, to replace long names with short names.

Which kind of names are too long for your tools? Let me break down the current situation:

Submodule instance names are generated based on the names from the source code, without any truncation. So if the user instantiated a register with a long name, then it would be long in the output Verilog. (Inlined module hierarchy is also added to the name, which can make it long.)

Similarly, the names of signals connecting to the ports of submodules are named "instance$port", without any truncation.

Signals which correspond to variables from the BSV source will also have the same name as in the source (plus a unique suffix). So these will be long if the source name is long.

For any other signals, BSC attempts to create a name from the expression. For example, a signal for the expression "x + y" would be named "x_PLUS_y" (again, with a unique suffix). These generated names are truncated to a maximum length, which is hardcoded at 50.

I believe those are all of the cases.

If we added a flag, the simplest thing would be for it to just control that "50" value, for generated names. To have BSC truncate other signals would require a more sophisticated pass, that would need to handle the name clashes that could arise from truncating long names with a similar prefix. Or suffix. Given that instance names start with the inlined hierarchy, it may make more sense to truncate from the beginning rather than the end. Or maybe from the middle. (The Workstation GUI would also need to be aware of the truncation, for presenting names and correlations to the waveforms.)

It also might make sense to do the truncation in different places, for the different types of names. Instance names are generated in the elaboration stage, which guarantees uniqueness by appending unique numbers when there are clashes. So we'd probably want to do the truncation there, before adding the suffix. For wire signals, it might be easier to truncate them later, in the Verilog back end.

So if you have some ideas of what you'd like to see, that would be helpful.

In the meantime, if you're only concerned about "reg" and "wire" signals (and you're not concerned about Workstation correlation), it seems like it would be easy to write a Perl script to process the Verilog. BSC declares all of the signals first, before the assign statements and always blocks, so a script could first get all of the names, then do a simple textual replacement of the rest of the file (no Verilog parsing needed), replacing the long names with shorter ones.
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