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Generating parametrized modules

 
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geschema



Joined: 17 Jan 2013
Posts: 4

PostPosted: Mon Jun 10, 2013 6:52 am    Post subject: Generating parametrized modules Reply with quote

I'm new to BSV, and I'm wondering whether it supports the generation of user-parametrizable Verilog modules. For example, when designing a FIFO in BSV, is there are way to have the depth of the FIFO configurable through a Verilog parameter, or does one have to set the value of the depth parameter in Bluespec before generating the Verilog?
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quark
Site Admin


Joined: 02 Nov 2007
Posts: 496

PostPosted: Tue Jun 11, 2013 3:41 pm    Post subject: Re: Generating parametrized modules Reply with quote

BSC can generate a very limited set of parameters, but mostly BSC cannot generate parameterized Verilog.

If you use the "parameter" keyword, BSC can generate Verilog with that argument as a parameter:
Code:
(* synthesize *)
module mkMod #(parameter Bit#(8) deviceID) (Ifc);

However, the parameter can't be used in any way that would conditionally instantiation submodules and it's can't be used to parameterize the width of ports or registers. So, for instance, you can't instantiate a parameterized number of registers -- for a FIFO depth, say. This capability is available in primitive (or imported) modules; so you can instantiate the primitive module "mkSizedFIFO" or "mkDepthParamFIFO", but you cannot currently write this type of module in BSV.

What you can do in BSV is to instantiate a max size and then use a parameter to control how much, up to that max, is used. (Or you can instantiate two modules and use a parameter to mux between them; but you can't use the parameter to instantiate only one of them.)
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geschema



Joined: 17 Jan 2013
Posts: 4

PostPosted: Wed Jun 12, 2013 2:30 pm    Post subject: Reply with quote

Thanks for your answer. I'm afraid that this makes it difficult to use BSV for commercial IP core development, where the end user expects a configurable Verilog module.
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 53

PostPosted: Mon Jul 01, 2013 12:23 pm    Post subject: Reply with quote

Just a few additional points for your consideration:

1. BSV has very powerful parameterization capabilities. You can parameterize, easily, on almost any dimension, including micro-architecture. This is facilitated by BSV's rule-based design, which enables the compiler to generate shared-resource scheduling/access management control logic automatically for you. This simplifies the expression and makes it significantly easier to parameterize on several dimensions.

Here's a description from the BSV by Example book: "BSV has much stronger parameterization, which directly a ffects everything: code size, code structure, code reuse, and code correctness. All types in BSV are rst-class, that is, one can write functions taking any types as arguments and any types as results. Modules and functions can be parameterized by other modules and functions; functions can generate Rules and Interfaces, and so on. This results in an unprecedented level of static elaboration expressive power (Turing complete 'generate')."

To get a feel, here are two references:

a) PAClib, which is a library for building parameterized datapaths. Here's a paper illustrating what you can do: http://www.bluespec.com/documents/Bluespec_PAClib_2010-01-07.pdf

b) Here's a paper that IBM Research wrote some years ago about building a parameterized PowerPC architecture model that runs in an FPGA (there are some code excerpts in the back highlighting some of the parameterization): http://domino.research.ibm.com/library/Cyberdig.nsf/papers/A70107DCCC6C06308525751B004C1BE5

2. Note that BSV can import RTL modules -- so your leaf modules, if written in RTL, could include 'generate' capabilities in them

3. Our customers with BSV tools have all the power of #1. If you need your customers to be able to set parameters and generate different Verilog versions, then we'd be happy to discuss some options to enable that.
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geschema



Joined: 17 Jan 2013
Posts: 4

PostPosted: Tue Jul 02, 2013 3:33 am    Post subject: Reply with quote

Thanks crimsoncardinal. It's perfectly clear to me that the parametrization capabilities of BSV itself are vastly superior to what RTL languages like VHDL or Verilog can offer.

I guess it's a common downside of all HLS tools that they can't generate fully parametrizable RTL code. Still, the benefits of BSV seem to far outweigh the limitations, so I will definitely consider BSV for my next FPGA projects and IP cores.

Many thanks,

Guy.
http://fpga-exchange.com
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