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simulating a bluespec wrapper for a verilog file in Xilinx

 
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zhangka



Joined: 12 Jun 2012
Posts: 17

PostPosted: Mon Jun 25, 2012 5:58 pm    Post subject: simulating a bluespec wrapper for a verilog file in Xilinx Reply with quote

Hi, I just wrote a Bluespec wrapper for a verilog file that is generated by Xilinx. I am trying to simulate this wrapper by writing another BSV file with the module mkBasic.

When I try to create a vsim Modelsim executable for this file to simulate it in Xilinx's iSim, it seems that a lot of the rules that I wrote in BSV to test the functionality of the wrapper is lost during the translation to verilog by looking at the generated file as the verilog file itself doesn't have many [email protected] blocks. As such, I have a verilog file that doesn't seem to do much as it has a lot of registers that are not instantiated (1010101010...) in verilog.

Help?
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quark
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Joined: 02 Nov 2007
Posts: 500

PostPosted: Tue Jun 26, 2012 6:13 pm    Post subject: Re: simulating a bluespec wrapper for a verilog file in Xili Reply with quote

BSV rules do not translate into always blocks in the generated Verilog. BSC in general does not create always blocks, except when they are required by the Verilog semantics (for instance, a case statement can only appear in an always block). So the absence of always blocks in your generated Verilog is not an indication of a problem. Can you show the BSV test module that you have written?
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