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Designing with BSV's Rules, Interfaces, ...
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No new posts module vs interface parameters
5 rasha 10896 Mon Jun 04, 2012 2:52 pm
quark View latest post
No new posts Synthesizing BSV Design in Xilinx ISE
2 kevin5k 6716 Sat Jun 02, 2012 3:18 am
kevin5k View latest post
No new posts BRAM Question
5 kvb 16513 Sat May 26, 2012 7:39 am
harish View latest post
No new posts Defining HW Constraints in Bluespec
2 kevin5k 6035 Thu May 10, 2012 7:13 am
kevin5k View latest post
No new posts Clock gating BSV library modules
1 madhav 4917 Wed May 09, 2012 3:32 pm
ewc View latest post
No new posts Generate bounded random numbers (Randomizable?)
2 Mohsen 6293 Mon Apr 30, 2012 10:47 am
Mohsen View latest post
No new posts 2012.01.A BRAMs are no longer inferred by Quartus II
1 erinaldo.pereira 5501 Tue Apr 17, 2012 9:27 pm
ShepSiegel View latest post
No new posts Opaque types in interfaces
5 mcadler 10723 Tue Apr 17, 2012 3:06 pm
mcadler View latest post
No new posts Synthesis boundary between BVI wrapper and the Verilog
0 rasha 5692 Sun Apr 15, 2012 8:47 pm
rasha View latest post
No new posts Indexing an array of BRAMs question
2 comododragon 6018 Sat Apr 14, 2012 1:10 am
comododragon View latest post
No new posts Using Vectors of Wires and interface methods
3 anthony_unisa 7150 Thu Apr 12, 2012 6:10 pm
anthony_unisa View latest post
No new posts Assign Actionvalue Vector
1 kevin5k 4461 Fri Apr 06, 2012 1:06 pm
quark View latest post
No new posts Logical partitioning of design/code (split rule precedence)
3 rasha 8884 Wed Apr 04, 2012 8:07 pm
quark View latest post
No new posts Clock gating in BVI wrappers (BVI doubts part.1)
3 rasha 7035 Mon Apr 02, 2012 1:33 am
quark View latest post
No new posts Unbound Variable
2 kevin5k 9626 Wed Dec 14, 2011 12:12 am
kevin5k View latest post
No new posts Optional parameters
2 mcadler 5407 Tue Dec 06, 2011 6:13 pm
mcadler View latest post
No new posts Synthesizable, parametrizable module port width
4 vennsa 6599 Fri Nov 18, 2011 7:01 pm
vennsa View latest post
No new posts Renewal of topic - use of AXI IP provided by Bluespec
2 ganeshgarg 7424 Tue Nov 15, 2011 8:01 am
ganeshgarg View latest post
No new posts Use of AXI IP provided by Bluespec
3 ganeshgarg 6975 Wed Nov 09, 2011 5:42 am
ganeshgarg View latest post
No new posts Why is Bit#(type n) more than bits?
2 chris 8329 Fri Oct 07, 2011 12:38 pm
chris View latest post
No new posts Type system: Not worth to learn the details?
1 chris 6867 Fri Sep 30, 2011 9:06 am
stoy View latest post
No new posts Review: Readable object behavior
2 chris 10733 Tue Sep 27, 2011 6:32 pm
chris View latest post
No new posts FILE OPERATIONS
1 RAMA RAJAN ATHISESHAN 5195 Tue Sep 27, 2011 5:06 pm
quark View latest post
No new posts Doubt regarding an example in the BSV by example book
3 chiraag 7574 Tue Sep 27, 2011 5:04 pm
stoy View latest post
No new posts -aggressive-conditions
1 patil.nikhil 6777 Tue Sep 27, 2011 5:04 pm
quark View latest post
No new posts Bluespec Scheduling
1 chiraag 5709 Tue Sep 27, 2011 4:32 pm
stoy View latest post
No new posts Assert Package broken?
3 chris 7513 Tue Sep 27, 2011 3:13 pm
stoy View latest post
No new posts import vs. `include and namespaces/scopes and similar stuff
1 rasha 5589 Fri Sep 02, 2011 3:50 pm
patil.nikhil View latest post
No new posts provisos and error T0079
5 rasha 10730 Tue Aug 30, 2011 1:26 pm
rasha View latest post
No new posts unbound constructor error
1 RAMA RAJAN ATHISESHAN 6781 Mon Jul 18, 2011 6:43 pm
quark View latest post
No new posts unbound constructor error
0 RAMA RAJAN ATHISESHAN 5822 Sat Jul 16, 2011 4:23 am
RAMA RAJAN ATHISESHAN View latest post
No new posts looking for LIFOF...
0 PhantomFav 5453 Sat Jul 09, 2011 6:06 am
PhantomFav View latest post
No new posts SyncFIFO synthesis issue
1 laplander 5695 Wed Jun 29, 2011 10:21 am
ewc View latest post
No new posts Designing a pipelined processor
1 saurav619 4945 Fri Jun 17, 2011 11:18 am
hadar_agam View latest post
No new posts Imporved Scheduling with the "Synthesize" tags
2 nharvey 6758 Sat May 07, 2011 8:45 am
nharvey View latest post
No new posts How to load and save files for simulation? Image Processing
0 Thadeu 6672 Thu Mar 24, 2011 7:10 am
Thadeu View latest post
No new posts generic inputs
2 dabox367 7229 Tue Mar 08, 2011 12:55 am
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No new posts Changing Resets
0 dabox367 6480 Tue Mar 08, 2011 12:50 am
dabox367 View latest post
No new posts how to convert Bit#(n) to Integer?
2 roMoon 11408 Mon Nov 15, 2010 10:33 am
roMoon View latest post
No new posts RevertingVirtualReg read gets optimized away
2 patil.nikhil 7582 Sat Oct 16, 2010 8:07 pm
patil.nikhil View latest post
No new posts sce-mi
1 madhav 7143 Mon Aug 02, 2010 8:19 pm
jnewbern View latest post
No new posts Data Flow modelling question
0 TheSheriff 6860 Thu Jun 10, 2010 1:22 am
TheSheriff View latest post
No new posts tradeoffs when using Real, Complex, or Math libraries
2 TheSheriff 7687 Thu Jun 10, 2010 1:01 am
TheSheriff View latest post
No new posts sce_mi pcie example
1 azeng 6468 Fri May 07, 2010 3:13 pm
crimsoncardinal View latest post
No new posts FSM Problem
2 justrajdeep 12118 Wed Apr 21, 2010 3:11 pm
baltus View latest post
No new posts Prelude.bs error
3 hrishikesh 13141 Fri Mar 19, 2010 1:45 pm
quark View latest post
No new posts Is it BSV support condition compile?
3 test002 8915 Mon Mar 15, 2010 11:18 pm
test002 View latest post
No new posts how to peform shift left or right operation ?
4 tyeowkwa 14330 Thu Mar 11, 2010 5:20 pm
tyeowkwa View latest post
No new posts Instruction set to memory
5 tyeowkwa 13313 Wed Mar 03, 2010 8:06 am
jnewbern View latest post
No new posts Multiple Resets
0 kirubi 7166 Thu Jan 28, 2010 5:18 am
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