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  Topic: applying conflict_free to all rules
zhangka

Replies: 8
Views: 8825

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Apr 03, 2013 4:24 pm   Subject: applying conflict_free to all rules
wow, thank you very much!
  Topic: applying conflict_free to all rules
zhangka

Replies: 8
Views: 8825

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Apr 03, 2013 3:22 pm   Subject: applying conflict_free to all rules
the idea that I had is that in the rule "move_pipe", the function movepipe() moves the data from pipeline stage "i" to stage i+1, constantly. Each stage would also have a bit, indi ...
  Topic: applying conflict_free to all rules
zhangka

Replies: 8
Views: 8825

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Apr 03, 2013 2:37 pm   Subject: applying conflict_free to all rules
ah alright, I'll look into it. I was using a DWire because I needed something to be "True" when the user calls the method, and then go back to "False" for the cycles that the metho ...
  Topic: applying conflict_free to all rules
zhangka

Replies: 8
Views: 8825

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Apr 03, 2013 1:36 pm   Subject: applying conflict_free to all rules
essentially I have the following code:


wire#(Bool) w_valid <- mkDWire(False)

rule getinput;
if (w_valid) $display("IT IS VALID");
valid ...
  Topic: applying conflict_free to all rules
zhangka

Replies: 8
Views: 8825

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Apr 01, 2013 11:48 pm   Subject: applying conflict_free to all rules
Hi,

I think by default, bsc is automatically adding a lot of logic to dictate the when each rule can fire, and I believe it is messing up my circuit by preventing some rules from firing.

Is ther ...
  Topic: Converting from a looped combinational path to pipelined
zhangka

Replies: 2
Views: 4653

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Sat Mar 30, 2013 4:30 pm   Subject: awesome
awesome, thanks quark!
  Topic: Converting from a looped combinational path to pipelined
zhangka

Replies: 2
Views: 4653

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Sun Mar 10, 2013 12:58 pm   Subject: Converting from a looped combinational path to pipelined
Hi, I currently have a circuitry that is made up of a combinational path that is looped multiple times (>50). In order to increase my throughput, I'm thinking of changing that into a pipelined desi ...
  Topic: simulating a bluespec wrapper for a verilog file in Xilinx
zhangka

Replies: 1
Views: 4128

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jun 25, 2012 5:58 pm   Subject: simulating a bluespec wrapper for a verilog file in Xilinx
Hi, I just wrote a Bluespec wrapper for a verilog file that is generated by Xilinx. I am trying to simulate this wrapper by writing another BSV file with the module mkBasic.

When I try to create a ...
  Topic: subinterfaces and method calling
zhangka

Replies: 4
Views: 8246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Jun 19, 2012 6:14 pm   Subject: subinterfaces and method calling
However, this bsv code I'm writing is simply a wrapper for a verilog file. As such, the methods I'm trying to call in a single rule are all methods that just feeds input into the verilog file, which s ...
  Topic: subinterfaces and method calling
zhangka

Replies: 4
Views: 8246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Jun 19, 2012 3:57 pm   Subject: subinterfaces and method calling
update:

if instead of doing the 2 method calls in 1 rule, I separate them into different rules, it works...
  Topic: subinterfaces and method calling
zhangka

Replies: 4
Views: 8246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Jun 19, 2012 3:50 pm   Subject: subinterfaces and method calling
Hi, so my code is laid out where my top most module has the interface x:

interface x;
interface y
interface z
endinterface

interface y;
method a
endinterface

interface z;
...
  Topic: Any easier way to write a BSV wrapper for a verilog code?
zhangka

Replies: 5
Views: 7443

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Jun 14, 2012 2:05 pm   Subject: Any easier way to write a BSV wrapper for a verilog code?
Thanks, I think I found the BSV wrapper I need for EMAC:

XilinxTEMAC.bsv.

However, are the verilog files for the wrapper and its dependencies come with Bluespec as well, or should I be generatin ...
  Topic: BSV wrappers for Xilinx cores
zhangka

Replies: 7
Views: 9955

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jun 13, 2012 5:13 pm   Subject: BSV wrappers for Xilinx cores
Does anyone know where the verilog files for the BSV wrappers that comes with BSV for Xilinx core are?

Or I'm I supposed to generate the verilog files myself through the Xilinx Core generator?

T ...
  Topic: example implementation using XilinxTEMAC wrapper?
zhangka

Replies: 0
Views: 4552

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jun 13, 2012 3:13 pm   Subject: example implementation using XilinxTEMAC wrapper?
anyone possess an implementation of the XilinxTEMAC wrapper so that I have a reference of how to send simple data via EMAC?
  Topic: Any easier way to write a BSV wrapper for a verilog code?
zhangka

Replies: 5
Views: 7443

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jun 13, 2012 3:10 pm   Subject: Any easier way to write a BSV wrapper for a verilog code?
oh wow, I found it there. Thanks!
 
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