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  Topic: Simulating bluespec converted to verilog in QuestaSim
quark

Replies: 4
Views: 108

PostForum: Tools: Other   Posted: Tue Oct 01, 2019 9:20 am   Subject: Simulating bluespec converted to verilog in QuestaSim
You ought to be able to debug the problem by looking at waveforms and relating the Verilog signals back to the source design. There is document in the Bluespec release, doc/BSV/bsv-verification-guide ...
  Topic: Simulating bluespec converted to verilog in QuestaSim
quark

Replies: 4
Views: 108

PostForum: Tools: Other   Posted: Tue Oct 01, 2019 9:12 am   Subject: Simulating bluespec converted to verilog in QuestaSim
Perhaps your design is never ready. Also, look for warnings during generation, as BSC can warn if a rule or method will never be ready because of scheduling conflicts. You can also look in the gener ...
  Topic: Simulating bluespec converted to verilog in QuestaSim
quark

Replies: 4
Views: 108

PostForum: Tools: Other   Posted: Mon Sep 30, 2019 2:04 pm   Subject: Simulating bluespec converted to verilog in QuestaSim
You cannot connect the Get and Put interfaces in this way. The protocol is: the RDY output indicates that the EN input may be asserted in the current clock cycle. In order to connect a Get and a Put ...
  Topic: Partially applied type synonym `Tuple3'
quark

Replies: 2
Views: 963

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Fri Feb 01, 2019 1:17 pm   Subject: Partially applied type synonym `Tuple3'
Your parentheses are not right in this type on that line:
Tuple3 #(Bool, Bit #(TLog #(num_slaves) , Bit #(TLog #(ids))))

It should be:
Tuple3 #(Bool, B ...
  Topic: Problem in ActionValue
quark

Replies: 1
Views: 2097

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Sep 20, 2018 1:51 pm   Subject: Re: Problem in ActionValue
Ordinary values can be assigned with equals-sign (=), but ActionValue must be assigned using left arrow (<-). The left arrow causes the Action part to be added to the actions of the rule while the ...
  Topic: Software Release
quark

Replies: 1
Views: 3235

PostForum: Software Releases   Posted: Thu Sep 20, 2018 1:38 pm   Subject: Re: Software Release
We no longer distribute the software via this forum. If you email [email protected], someone can give you a link to download the latest release.
  Topic: CReg
quark

Replies: 1
Views: 2126

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jul 09, 2018 6:14 pm   Subject: Re: CReg
It sounds like you are missing the bracket index for selecting from the Array of Reg interfaces.

You probably have something like this in your code:
vect_reg1_s[vec_idx].pg4Ks
but you nee ...
  Topic: High impedance TriState Element
quark

Replies: 2
Views: 3792

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Dec 05, 2017 5:35 pm   Subject: Re: High impedance TriState Element
The "mkTriState" module is an imported Verilog module in the file "TriState.v", and that module does not appear to provide a valid signal, only the value.

I agree that it would ...
  Topic: Convert a vector to a register
quark

Replies: 1
Views: 3919

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Fri Aug 18, 2017 5:10 pm   Subject: Re: Convert a vector to a register
You can declare a local variable, which can be written to multiple times, and then you can commit the final value to the register in one write. For example:
Vector#(4,Reg#(Bit#(1) ...
  Topic: Define struct with a module element
quark

Replies: 3
Views: 6076

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Feb 21, 2017 4:55 pm   Subject: Define struct with a module element
Yes, the variable "c" isn't mentioned.

When someone defines a new module type, they have to define an instance of the "IsModule" typeclass, which says how ordinary modules (of t ...
  Topic: Define struct with a module element
quark

Replies: 3
Views: 6076

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Feb 20, 2017 5:47 pm   Subject: Re: Define struct with a module element
This internal error occurs whenever you use the special type "module" outside of a "module..endmodule" block. (We will eventually make it a more helpful user error.)

Ordinary m ...
  Topic: Extending TieOff
quark

Replies: 3
Views: 6198

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Oct 17, 2016 9:54 pm   Subject: Extending TieOff
Did you have to define an instance of TieOff for Get? I don't see an instance that's pre-defined in the library. The TieOff package shows an example of using it for Get, in a comment, but doesn't ac ...
  Topic: Extending TieOff
quark

Replies: 3
Views: 6198

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Oct 17, 2016 3:29 pm   Subject: Re: Extending TieOff
What is the type of the interface that you want to tie off? You say "ports", but you're not referring to a Verilog output port, right?

And do you really mean "TieOff"? or do yo ...
  Topic: Defining a type function
quark

Replies: 2
Views: 5891

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Oct 03, 2016 4:34 pm   Subject: Re: Defining a type function
BSC doesn't currently have a way to create a type function like you're asking for.

Also, unfortunately, BSC doesn't currently support provisos on interface types. Otherwise, you could write this: ...
  Topic: Infeasible Ramstyle in Vivado
quark

Replies: 3
Views: 13274

PostForum: Tools: Other   Posted: Sun Sep 11, 2016 3:51 pm   Subject: Re: Infeasible Ramstyle in Vivado
The Bluespec release includes a directory of alternate Verilog files that you should use when synthesizing with Vivado. It is located at $BLUESPECDIR/Verilog.Vivado/ instead of $BLUESPECDIR/Verilog/. ...
 
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