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  Topic: libgmp 3
oarcas

Replies: 1
Views: 6760

PostForum: Tools: BSC (Bluespec Compiler)   Posted: Tue Jul 28, 2015 8:33 am   Subject: libgmp 3
Hi,

I am currently using BSV 2014.07.A on Ubuntu 14.04 LTS.

BSC requires libgmp.so.3. In Ubuntu 14.04 this library doesn't exist any more, it's been replaced with libgmp.so.10. This makes BSC un ...
  Topic: Method guard and scheduling
oarcas

Replies: 1
Views: 4593

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jun 17, 2015 9:10 am   Subject: Method guard and scheduling
Hello,

I did not find any previous post discussing about this, but maybe I am repeating a question.

I have a module with a guarded method and a guarded rule like the following:


Reg#(Bit ...
  Topic: Buggy SizedFIFO when using Xilinx XST and BlockRAM
oarcas

Replies: 4
Views: 9343

PostForum: Tools: BSC (Bluespec Compiler)   Posted: Wed Dec 31, 2014 10:14 am   Subject: Buggy SizedFIFO when using Xilinx XST and BlockRAM
I am porting the design to a Virtex 7 with Vivado 2014.4. I'll check if the issue persists.

BTW, I found a BSV source in BLUESPEC_DIR/Verilog.Vivado/SizedFIFO.v with the same modification I describ ...
  Topic: Buggy SizedFIFO when using Xilinx XST and BlockRAM
oarcas

Replies: 4
Views: 9343

PostForum: Tools: BSC (Bluespec Compiler)   Posted: Sun Dec 21, 2014 9:18 am   Subject: Buggy SizedFIFO when using Xilinx XST and BlockRAM
Hi,

I wanted to raise attention about SizedFIFOs as BlockRAMs in Xilinx FPGAs. This topic was addressed in another post ((* RAM_STYLE = "distributed" *)
reg [p1width - 1 : ...
  Topic: Verilog attributes
oarcas

Replies: 2
Views: 9860

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Sun Dec 21, 2014 8:40 am   Subject: Re: Verilog attributes
Hi Quark. With a bit of delay, thanks for your reply.

Recently I needed to mark some registers as "KEEP = TRUE", so I revisited this topic. I share how I implemented the (* doc *)-based s ...
  Topic: Verilog attributes
oarcas

Replies: 2
Views: 9860

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jul 21, 2014 10:20 am   Subject: Verilog attributes
Hi,

Is it possible to put attributes to BSV modules (wires, registers, etc.) so that these attributes remain in the Verilog code?

I don't know if this feature exists, but it would be very useful ...
  Topic: Error: negated pattern matching in rule's guard
oarcas

Replies: 2
Views: 7306

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jun 30, 2014 11:27 am   Subject: Re: Error: negated pattern matching in rule's guard
Thank you for your answer, I will try these methods.

Oriol
  Topic: Error: negated pattern matching in rule's guard
oarcas

Replies: 2
Views: 7306

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Fri Jun 20, 2014 11:35 am   Subject: Error: negated pattern matching in rule's guard
Hi,

When I use pattern matching in a rule's guard, it works fine:

rule r1 ( fifo.first matches tagged TAG_A .v );

I also want rule r2 to not trigger in that particular case:

rule r ...
  Topic: BSV syntax coloring template for Gedit (GNU/Linux)
oarcas

Replies: 5
Views: 17789

PostForum: Tools: Other   Posted: Tue Jun 07, 2011 2:06 pm   Subject: BSV syntax coloring template for Gedit (GNU/Linux)
Hi,

I've just created a syntax coloring template of BSV for Gedit (the default text editor of Gnome) that makes my life easier and happier.

Just copy it to /usr/share/gtlsourceview-2.0/language- ...
 
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