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  Topic: Multiple Resets
kirubi

Replies: 0
Views: 6893

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Jan 28, 2010 5:18 am   Subject: Multiple Resets
Hello

I have a question

How do I do the following in BSV.

A four bit register say n_reg whose reset values differ based on two different resets say a_rst and b_rst.Both are asynchronous reset ...
  Topic: Multiple-clocks and ancestor_of attributes
kirubi

Replies: 0
Views: 7426

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Dec 29, 2009 10:56 am   Subject: Multiple-clocks and ancestor_of attributes
Hello

How do I go about doing this in blue-spec

I have two clocks say clk1khz and clk100khz which are inputs.clk1khz can be treated as default_clock and I have reset input reset_in

A counter ...
  Topic: Resets
kirubi

Replies: 3
Views: 8401

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Dec 28, 2009 10:04 pm   Subject: Resets
Thanks once again quark.

My idea is to use couple of reset signals that are generated inside and also provided from outside the module.

For example in certain scenarios you may want to trigger a ...
  Topic: What does this error mean?
kirubi

Replies: 1
Views: 6127

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Fri Dec 25, 2009 8:01 am   Subject: What does this error mean?
Error: "Clocks.bsv", line 1679, column 9: (G0005)
The assertion `clock_crossing_rule' failed for rule `clock_domain_crossing'
because it has an implicit condition

best
Venkat
  Topic: Resets
kirubi

Replies: 3
Views: 8401

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Dec 24, 2009 11:51 pm   Subject: Resets
Hello

Can anyone provide any examples for isResetAsserted? and isAsserted?

best
Venkat
  Topic: conv_integer
kirubi

Replies: 8
Views: 16246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Dec 16, 2009 12:54 am   Subject: conv_integer
Hello nikhil

The discussion is about getting blue-spec equivalent of conv_integer library function in vhdl.

There is no conv_integer in verilog and hence blue-spec yes.. but some $ functions lik ...
  Topic: conv_integer
kirubi

Replies: 8
Views: 16246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Dec 15, 2009 12:45 am   Subject: conv_integer
Thank you quark

Yes I have tried both.. But the synthesis (hardware) output is not the same as I get with vhdl equivalent with conv_integer function.

So I was wondering if it really would make ...
  Topic: conv_integer
kirubi

Replies: 8
Views: 16246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Dec 14, 2009 8:36 pm   Subject: conv_integer
Thanks Quark.

My requirement is as follows

I have a 6 bit input-addr_in and a corresponding 32 bit output-addr_out.

Let us simply say this is a decoder.

If my 6 bit input say addr_in = 6' ...
  Topic: conv_integer
kirubi

Replies: 8
Views: 16246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Dec 14, 2009 11:22 am   Subject: conv_integer
let us say I have a six bit value stored in "address"
(example address = 6'b000101 a conv_integer(address) will return Integer 5.

(i.e) the conv_integer function of vhdl exactly converts ...
  Topic: conv_integer
kirubi

Replies: 8
Views: 16246

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Dec 14, 2009 11:11 am   Subject: conv_integer
Is there blue-spec equivalent of conv_integer function in VHDL?

best
Venkat
  Topic: generating multiple clocks from a bsv module
kirubi

Replies: 2
Views: 7625

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Oct 26, 2009 8:59 am   Subject: generating multiple clocks from a bsv module
I think we can have method Clock clock1();

Then declare a Clock divider interface

ClockDividerIfc clock1<-mkClockDivider(10);

so on and each method will return something like

method C ...
  Topic: generating multiple clocks from a bsv module
kirubi

Replies: 2
Views: 7625

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Oct 26, 2009 3:49 am   Subject: generating multiple clocks from a bsv module
Hello

How do we go about generating multiple clock outputs from a single bsv module.?

Each clock generated is /10 clock of the previous one.

(ie) The first clock is /10 of the bsv system cloc ...
 
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