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  Topic: Generating parametrized modules
geschema

Replies: 4
Views: 10067

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Jul 02, 2013 3:33 am   Subject: Generating parametrized modules
Thanks crimsoncardinal. It's perfectly clear to me that the parametrization capabilities of BSV itself are vastly superior to what RTL languages like VHDL or Verilog can offer.

I guess it's a commo ...
  Topic: Generating parametrized modules
geschema

Replies: 4
Views: 10067

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jun 12, 2013 2:30 pm   Subject: Generating parametrized modules
Thanks for your answer. I'm afraid that this makes it difficult to use BSV for commercial IP core development, where the end user expects a configurable Verilog module.
  Topic: Generating parametrized modules
geschema

Replies: 4
Views: 10067

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jun 10, 2013 6:52 am   Subject: Generating parametrized modules
I'm new to BSV, and I'm wondering whether it supports the generation of user-parametrizable Verilog modules. For example, when designing a FIFO in BSV, is there are way to have the depth of the FIFO c ...
  Topic: Bluespec tools on Microsoft Windows
geschema

Replies: 1
Views: 7534

PostForum: Tools: BSC (Bluespec Compiler)   Posted: Fri Jan 18, 2013 4:55 am   Subject: Bluespec tools on Microsoft Windows
What's the best way to run the Bluespec tools on a Windows 7 machine? Has anyone had any success with Cygwin, or do I need to use a virtual machine running a Linux OS?
 
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