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  Topic: Writing a Wrapper module
gagan

Replies: 3
Views: 6778

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Jun 04, 2015 6:19 am   Subject: HI
Hi Quark,
Thanks for reply .
I am doing like ...

module mkEmptymodule(ApbBusIfc);

endmodule:mkEmptymodule
  Topic: Writing a Wrapper module
gagan

Replies: 3
Views: 6778

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jun 03, 2015 4:42 am   Subject: Writing a Wrapper module
i have a top module which has some interfaces passed to it as argument, and its interface is Empty


module mkBusFabric#(BusIfc a )


and since cant be synthesized, So to synthesize it, ...
  Topic: Segmentation Fault Issue
gagan

Replies: 1
Views: 6679

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue May 19, 2015 4:54 am   Subject: Segmentation Fault Issue
The thing is , If i only do compile , design compiles without throwing any error
If i do Complle + Link , compiler gives segmentation fault.

sh: line 1: 18933 Segmentation fault (core dumped) ...
  Topic: Using SyncReg for interfacing two cloclk domains
gagan

Replies: 1
Views: 5380

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Apr 16, 2015 11:42 pm   Subject: Using SyncReg for interfacing two cloclk domains
I want to design a module , which interface two different clock domains,kind of bridge
So to start with, I wrote two modules , one just updates the synch reg and the other reads from the synch reg. ...
  Topic: XST678 : Cannot evaluate constant
gagan

Replies: 4
Views: 8759

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Apr 15, 2015 1:27 am   Subject: Sharing design files
Hi Quark,

Can i have your mail id to share my design files.

Thanks,
Gagan
  Topic: Clock Divider in BSV (the ration is not an Integer)
gagan

Replies: 4
Views: 11736

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Feb 24, 2015 1:31 am   Subject: To take generated clock output as input to other modules
Hi,
I have made a clock divider and according to logic it is switching between
clk_gen.setClockValue(0); and clk_gen.setClockValue(1);
.

Now i want this new clock as the output of clk divid ...
  Topic: Defining a 2D Vector
gagan

Replies: 4
Views: 9729

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Feb 10, 2015 5:14 am   Subject: Using defaultValue for a Vector
Hi Quark
Thanks for the solution, I found Default Value class in reference guide, and an example was provided for using defaultvalue for a custom structure.

However , in my case, I have a vector ...
  Topic: Defining a 2D Vector
gagan

Replies: 4
Views: 9729

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Feb 09, 2015 3:37 am   Subject: The provisos for this expression could not be resolved
What i am doing is :-

Vector#(Set_Count,Vector#(Set_Association,Reg#(Cache_Line))) cache_blk <-replicateM(replicateM (mkReg(0)));

where Cache Line is a struct declared as:-

typedef str ...
  Topic: Defining a 2D Vector
gagan

Replies: 4
Views: 9729

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Feb 09, 2015 1:24 am   Subject: Defining a 2D Vector
HI..
I want to define a 2 D vector...for a cache design(set associative)

So i am thinking like...all the sets make a column
and while all the different Tags (in a set ) make a row..

So i am w ...
  Topic: BRAM initialization from a file
gagan

Replies: 4
Views: 13302

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jan 28, 2015 2:08 am   Subject: Thanks...
Thanks Qaurk.

Well, the issue i am getting now is not related to bluespec but verilog.
The thing is , the Memory is getting initialized to XXXX(don't care) in simulation
I am following the code g ...
  Topic: BRAM initialization from a file
gagan

Replies: 4
Views: 13302

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Jan 27, 2015 8:25 am   Subject: BRAM initialization from a file
Hi..
I want to initialize BRAM from a file.

the information i have obtained till now , is as follows:-

String filename = "memory_file.hex";
BRAM_Configure bram_cfg = defa ...
  Topic: Registers as Clocks
gagan

Replies: 8
Views: 15870

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Jan 07, 2015 5:55 am   Subject: using a newly drived clock in a submodule
In top module, I genrated a new clock as "clk" ...
now i want a submodule to use that newly genrated clock
I am doing like :-

UartCIfc uartcore <-mkUartC(False,clocked_by clk);
wh ...
  Topic: Registers as Clocks
gagan

Replies: 8
Views: 15870

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Tue Jan 06, 2015 5:44 am   Subject: Thanks...
Thanks Quark .
...I found two changes to be done...

MakeClockIfc#(Bit#(1)) clk_gen <- mkUngatedClock(0);
Clock clk = clk_gen.new_clk instead of Clock clk = clk_gen.new_clock.
  Topic: XST678 : Cannot evaluate constant
gagan

Replies: 4
Views: 8759

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jan 05, 2015 6:37 am   Subject: The BRAM 1 file is synthesizing , if set as top module
Hi Quark,

I Found that BRAM 1 file is synthesizing , if set as top module.
So there is problem in the other files.

Thanks..
  Topic: Registers as Clocks
gagan

Replies: 8
Views: 15870

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Mon Jan 05, 2015 6:35 am   Subject: Using setClockValue & getClockValue
I want to know the syntax for using setClockValue,getClockValue,

is it like:-
Clock clk;

clk.setClockValue(1'b1);

reference guide should have some example.
 
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