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  Topic: Active-low enable signal in RTL
NoOne

Replies: 2
Views: 5509

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Mar 13, 2013 1:58 pm   Subject: Active-low enable signal in RTL
Thanks, that is indeed what I'm currently doing, just wanted to know if there was a more straightforward way to do it.
  Topic: Active-low enable signal in RTL
NoOne

Replies: 2
Views: 5509

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Wed Mar 13, 2013 9:11 am   Subject: Active-low enable signal in RTL
Hello,
I am trying to import a verilog module into BSC.
One of the methods I wish to implement has a corresponding "enable" signal in the verilog module, however, it is an active-low enabl ...
  Topic: Numeric type definition
NoOne

Replies: 7
Views: 17829

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Sun Dec 30, 2012 6:17 pm   Subject: Numeric type definition
Thanks for the reply.
Your example helped clarify the recursive use of the typeclass definition.
The example I gave was just to have a simple illustration of the issue, I can easily expand it to hav ...
  Topic: Numeric type definition
NoOne

Replies: 7
Views: 17829

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Dec 27, 2012 5:19 pm   Subject: Thanks
Hi Quark,
Thank you very much for your reply.
Your last example actually solves many of my issues, I wasn't aware you could use a List in a synthesizable module. That indeed lets me pass an Integer ...
  Topic: Numeric type definition
NoOne

Replies: 7
Views: 17829

PostForum: Designing with BSV's Rules, Interfaces, ...   Posted: Thu Dec 27, 2012 12:10 am   Subject: Numeric type definition
Hi,
I was wondering if there was any way to define a numeric type as an explicit parameter to a module.
I know I can use a "fake" size n bit vector for example as a parameter to implicitly ...
 
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